# US 9,437,716 B2 · Semiconductor device comprising a graphene wire > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,716 B2 - Document ID: US9437716B2 - Status: Granted - Kind: B2 - Application number: 14/803,751 - Filed: 2015-07-20 - Published: 2015-11-12 - Granted: 2016-09-06 - Earliest claimed: 2012-09-21 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Kabushiki Kaisha Toshiba - Inventors: Makoto Wada; Yuichi Yamazaki; Akihiro Kajita; Atsunobu Isobayashi; Tatsuro Saito - Web page: https://patentgrep.com/patent/US9437716B2 ## CPC - H10D 48/383: {Quantum effect devices, e.g. of devices using quantum reflection, diffraction or interference effects} - B82Y 30/00: Nanotechnology for materials or surface science, e.g. nanocomposites - H10W 20/43: Layouts of interconnections - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10W 20/4462: {Carbon or carbon-containing materials, e.g. graphene} - C01B 32/186: by chemical vapour deposition [CVD] - Y10S 977/734: Fullerenes, i.e. graphene-based structures, such as nanohorns, nanococoons, nanoscrolls or fullerene-like structures, e.g. WS2 or MoS2 chalcogenide nanotubes, planar C3N4, etc. - Y10S 977/932: for electronic or optoelectronic application - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - C01B: NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; {METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C} - Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS ## Abstract According to one embodiment, a semiconductor device includes a catalyst underlying layer formed on a substrate including semiconductor elements formed thereon and processed in a wiring pattern, a catalyst metal layer that is formed on the catalyst underlying layer and whose width is narrower than that of the catalyst underlying layer, and a graphene layer growing with a sidewall of the catalyst metal layer set as a growth origin and formed to surround the catalyst metal layer. ## Claims ### Claim 1 A semiconductor device comprising: a metal layer provided above a substrate comprising a semiconductor element, the metal layer extending in a first longitudinal direction and having a convex cross-sectional surface in a plane perpendicular to the first longitudinal direction; and a graphene layer provided on the metal layer to surround a side surface and an upper surface of a convex portion of the metal layer, the graphene layer having a curved cross-sectional surface and extending in the first longitudinal direction, wherein the metal layer comprises a first portion which is flat and a second portion which is convex, and wherein the second portion has a tapered shape whose widths of upper and lower surfaces are different, and has surface (111) alignment. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the first portion is an underlying layer, and the second portion is a catalyst layer. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein an end portion of the graphene layer contacts at least one of an upper surface of the first portion and a side surface of the second portion. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein a facet is provided on a side surface of the second portion, and an end portion of the graphene layer contacts the facet. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the upper surface of the second portion is narrower than the lower surface of the second portion. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the graphene layer is formed in a roll shape. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein the metal layer comprises a first portion which is flat and a second portion which is convex, and a width of the first portion is set according to a required roll diameter of the graphene layer. ### Claim 8 A semiconductor device comprising: a metal layer provided above a substrate comprising a semiconductor element, the metal layer extending in a first longitudinal direction; and a graphene layer provided on the metal layer to surround a side surface and an upper surface of the metal layer, the graphene layer extending in the first longitudinal direction and having a convex cross-sectional surface with respect to the metal layer in a plane perpendicular to the first longitudinal direction, wherein the metal layer comprises a first portion having a first width and including the upper surface, and a second portion which is provided on the first portion and which has a second width smaller than the first width, the second portion having a tapered shape whose widths of upper and lower surfaces are different, and has surface (111) alignment, and wherein the graphene layer comprises a plurality of graphene sheets which are stacked, and a portion of end portions of the graphene sheets is in contact with the upper surface of the first portion of the metal layer. ### Claim 9 (depends on 8) The semiconductor device of claim 8, wherein the first portion is an underlying layer, and the second portion is a catalyst layer. ### Claim 10 (depends on 8) The semiconductor device of claim 8, wherein a facet is provided on a side surface of the second portion, and another portion of end portions of the graphene sheets is in contact with the facet. ### Claim 11 (depends on 8) The semiconductor device of claim 8, wherein the upper surface of the second portion is narrower than the lower surface of the second portion. ### Claim 12 (depends on 8) The semiconductor device of claim 8, wherein the graphene layer is formed in a roll shape. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein the width of the first portion is set according to a required roll diameter of the graphene layer.