# US 9,437,713 B2 · Devices and methods of forming higher tunability FinFET varactor

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- Number: US 9,437,713 B2
- Document ID: US9437713B2
- Status: Granted
- Kind: B2
- Application number: 14/181,790
- Filed: 2014-02-17
- Published: 2015-08-20
- Granted: 2016-09-06
- Earliest claimed: 2014-02-17
- Assignees: Globalfoundries Inc.
- Applicants: Globalfoundries Inc.
- Inventors: Jagar Singh; Andy Wei; Gopal Srinivasan; Amaury Gendron
- Web page: https://patentgrep.com/patent/US9437713B2

## CPC

- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 1/66: Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 84/813: {Combinations of field-effect devices and capacitor only}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Devices and methods for forming semiconductor devices with wider FinFETs for higher tunability of the varactor are provided. One method includes, for instance: obtaining an intermediate semiconductor device; applying a spacer layer over the semiconductor device; etching the semiconductor device to remove at least a portion of the spacer layer to expose the plurality of mandrels; removing the mandrels; etching the semiconductor device to remove a portion of the dielectric layer; forming at least one fin; and removing the spacer layer and the dielectric layer. One intermediate semiconductor device includes, for instance: a substrate; a dielectric layer over the substrate; a plurality of mandrels formed on the dielectric layer, the mandrels including a first set of mandrels and a second set of mandrels, wherein the first set of mandrels have a width twice as large as the second set of mandrels; and a spacer layer applied over the mandrels.

## Claims

### Claim 1

A method comprising:
obtaining an intermediate semiconductor device, comprising:
a substrate;
a dielectric layer over the substrate; and
a plurality of mandrels formed on the dielectric layer;
applying a spacer layer over the intermediate semiconductor device;
etching the intermediate semiconductor device to remove a horizontal portion of the spacer layer to form at least one vertical portion of the spacer layer and to expose a top surface of the plurality of mandrels, the at least one vertical portion of the spacer layer comprising:
a first set of spacers with a first width; and
a second set of spacers with a second width, wherein the first width is about twice the size as the second width;
removing the plurality of mandrels;
etching the intermediate semiconductor device to remove at least a portion of the dielectric layer to form a first set of masks under the first set of spacers and a second set of masks under the second set of spacers;
forming at least one first fin and at least one second fin, wherein the intermediate semiconductor device now comprises:
a portion of the substrate;
the at least one first fin extending above the portion of the substrate, the at least one first fin having a first fin width;
the at least one second fin extending above the portion of the substrate, the at least one second fin having a second fin width and wherein the first fin width is about twice the size of the second fin width;
the first set of masks positioned on the at least one first fin;
the second set of masks positioned on the at least one second fin;
the first set of spacers positioned on the first set of masks; and
the second set of spacers positioned on the second set of masks; and
removing the at least one vertical portion of the spacer layer and the dielectric layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first set of spacers remaining after removing the plurality of mandrels is a double spacer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the double spacer has a width ranging from about 10 nm to about 20 nm for a 20 nm technology node.

### Claim 4 (depends on 1)

The method of claim 1, wherein the at least one fin has a double fin width.

### Claim 5 (depends on 4)

The method of claim 4, wherein the double fin width ranges from about 10 nm to about 40 nm.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
forming a gate over the at least one fin.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
forming at least one contact over the gate; and
forming at least one contact over the at least one fin.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
doping the at least one fin.

### Claim 9 (depends on 8)

The method of claim 8, wherein doping the at least one fin comprises:
implanting n+ into the at least one fin.

### Claim 10 (depends on 8)

The method of claim 8, wherein doping the at least one fin comprises:
implanting p+ into the at least one fin.

### Claim 11 (depends on 1)

The method of claim 1, wherein the at least one first fin comprises:
a bottom portion adjacent to the portion of the substrate; and
a top portion on top of the bottom portion, wherein a width of the at least one first fin gradually increases from the top portion to the bottom portion; and
wherein the at least one second fin comprises:
a bottom portion adjacent to the portion of the substrate; and
a top portion on top of the bottom portion, wherein a width of the at least one second fin gradually increases from the top portion to the bottom portion.