# US 9,437,708 B2 · Enhancement mode III-N HEMTs

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- Number: US 9,437,708 B2
- Document ID: US9437708B2
- Status: Granted
- Kind: B2
- Application number: 14/945,341
- Filed: 2015-11-18
- Published: 2016-03-10
- Granted: 2016-09-06
- Earliest claimed: 2008-04-23
- Assignees: Transphorm Inc.
- Applicants: Transphorm Inc.
- Inventors: Umesh Mishra; Robert Coffie; Likun Shen; Ilan Ben-Yaacov; Primit Parikh
- Web page: https://patentgrep.com/patent/US9437708B2

## CPC

- H10D 30/4735: {having delta-doped or planar-doped donor layers}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/4732: {using Group III-V semiconductor material}
- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 30/477: {Vertical HEMTs or vertical HHMTs}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 62/605: {Planar doped, e.g. atomic-plane doped or delta-doped}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 62/854: further characterised by the dopants
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10P 14/3416: {Nitrides}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.

## Claims

### Claim 1

A method of forming a III-N semiconductor device, comprising:
forming a nitride channel layer, the composition of the nitride channel layer being selected from the group consisting of nitrides of gallium, indium, aluminum, and combinations thereof;
forming an AlXN layer adjacent the channel layer in the areas adjacent to the channel access regions but not in the area adjacent to the first channel region, wherein X is selected from the group consisting of gallium, indium or their combination; and
forming a gate, wherein the nitride channel layer includes a first channel region beneath the gate, and channel access regions on opposite sides of the first channel region; wherein
the concentration of Al and thickness of the AlXN layer is selected to induce a 2DEG charge in the channel access regions adjacent the AlXN layer without inducing any substantial 2DEG charge in the first channel region, so that a channel comprising the 2DEG charge is not conductive in the absence of a switching voltage applied to the gate, but is conductive when a switching voltage greater than a device threshold voltage is applied to the gate.

### Claim 2 (depends on 1)

The method of claim 1, wherein the AlXN layer is n-doped.

### Claim 3 (depends on 2)

The method of claim 2, wherein the n-dopant is Si.

### Claim 4 (depends on 1)

The method of claim 1, wherein the III-N semiconductor device includes a substrate, and the method further comprises forming an additional nitride layer between the substrate and the nitride channel layer, the additional nitride layer being selected from the group consisting of nitrides of gallium, indium, aluminum, and combinations thereof, wherein the nitride channel layer comprises GaN.

### Claim 5 (depends on 4)

The method of claim 4, wherein the additional nitride layer comprises AlGaN.

### Claim 6 (depends on 1)

The method of claim 1, further comprising forming an insulator layer between the gate and the nitride channel layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein the insulator layer includes SiN.

### Claim 8 (depends on 6)

The method of claim 6, further comprising forming source and drain contacts at opposite ends of the channel.

### Claim 9 (depends on 8)

The method of claim 8, wherein the insulator layer extends from the source contact to the drain contact.

### Claim 10 (depends on 1)

The method of claim 1, further comprising forming a second AlXN layer between the AlXN layer and the channel layer, the second AlXN layer having a substantially higher concentration of Al than the AlXN layer.

### Claim 11

A method forming a III-N semiconductor device, comprising:
forming a nitride channel layer including a first channel region beneath a conductive gate contact, and channel access regions on opposite sides of the first channel region, the composition of the nitride channel layer being selected from the group consisting of nitrides of gallium, indium, aluminum, and combinations thereof;
forming an AlXN layer over the channel layer, wherein X is selected from the group consisting of gallium, indium or their combination; and
forming an aperture in the AlXN layer in a gate region of the device, and forming an insulator covering at least part of the aperture; wherein
the conductive gate contact is over the insulator and insulated from the AlXN layer; and
the Al concentration and thickness of the AlXN layer is selected such that a 2DEG charge is induced in the channel access regions adjacent the AlXN layer without inducing any substantial 2DEG charge in the first channel region, so that a channel comprising the 2DEG charge is not conductive in the absence of a switching voltage applied to the conductive gate contact, but is conductive when a switching voltage greater than a threshold voltage is applied to the conductive gate contact.

### Claim 12 (depends on 11)

The method of claim 11, wherein the aperture has slanted sides.

### Claim 13 (depends on 11)

The method of claim 11, further comprising forming conductive source and drain contacts on opposite sides of the conductive gate contact.

### Claim 14 (depends on 11)

The method of claim 11, wherein the AlXN layer is n-doped.

### Claim 15 (depends on 14)

The method of claim 14, wherein the n-dopant is Si.

### Claim 16 (depends on 11)

The method of claim 11, wherein the III-N semiconductor device includes a substrate, and the method further comprises forming an additional nitride layer between the substrate and the nitride channel layer, the additional nitride layer being selected from the group consisting of nitrides of gallium, indium, aluminum, and combinations thereof, wherein the nitride channel layer comprises GaN.

### Claim 17 (depends on 16)

The method of claim 16, wherein the additional nitride layer comprises AlGaN.

### Claim 18

A method of forming a III-N semiconductor device, comprising:
forming a nitride channel layer including a first channel region beneath a recessed gate region and channel access regions on opposite sides of the first channel region, the channel access regions respectively connected to a source and a drain, the composition of the nitride channel layer being selected from the group consisting of nitrides of gallium, indium, aluminum, and combinations thereof;
forming a III-N layer adjacent the nitride channel layer and surrounding the recessed gate region;
forming an AlmYN layer adjacent to the III-N layer and surrounding the recessed gate region, wherein Y is selected from the group consisting of gallium, indium or their combination; and
forming a gate in the recessed gate region; wherein
the first channel region is non-conductive in the absence of a switching voltage applied to the gate, but is conductive in the presence of a switching voltage greater than a threshold voltage applied to the gate.

### Claim 19 (depends on 18)

The method of claim 18, wherein the III-N semiconductor device includes a substrate, and the method further comprises forming an additional nitride layer between the substrate and the nitride channel layer, the additional nitride layer being selected from the group consisting of nitrides of gallium, indium, aluminum, and combinations thereof, wherein the nitride channel layer comprises GaN.

### Claim 20 (depends on 18)

The method of claim 18, further comprising forming a gate insulator layer between the gate and the nitride channel layer.

### Claim 21 (depends on 20)

The method of claim 20, wherein the gate insulator layer includes SiN.

### Claim 22 (depends on 20)

The method of claim 20, wherein the gate insulator layer extends from the source to the drain.