# US 9,437,707 B2 · Transistors with isolation regions

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- Number: US 9,437,707 B2
- Document ID: US9437707B2
- Status: Granted
- Kind: B2
- Application number: 14/810,906
- Filed: 2015-07-28
- Published: 2015-11-19
- Granted: 2016-09-06
- Earliest claimed: 2010-12-15
- Assignees: Transphorm Inc.
- Applicants: Transphorm Inc.
- Inventors: Umesh Mishra; Srabanti Chowdhury
- Web page: https://patentgrep.com/patent/US9437707B2

## CPC

- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/517: {characterised by the conducting layers}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 62/854: further characterised by the dopants
- H10D 64/111: {Field plates}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A transistor device is described that includes a source, a gate, a drain, a semiconductor material which includes a gate region between the source and the drain, a plurality of channel access regions in the semiconductor material on either side of the gate, a channel in the semiconductor material having an effective width in the gate region and in the channel access regions, and an isolation region in the gate region. The isolation region serves to reduce the effective width of the channel in the gate region without substantially reducing the effective width of the channel in the access regions. Alternatively, the isolation region can be configured to collect holes that are generated in the transistor device. The isolation region may simultaneously achieve both of these functions.

## Claims

### Claim 1

A method of forming a transistor device, comprising:
forming a source, a gate, and a drain on a III-N semiconductor material, the III-N semiconductor material having a channel therein, the III-N semiconductor material including a gate region between the source and the drain and a plurality of channel access regions between the source and the gate and between the drain and the gate, respectively; and
forming a plurality of isolation regions in the III-N semiconductor material, the plurality of isolation regions serving to improve the efficiency of hole collection from the III-N semiconductor material; wherein
the plurality of isolation regions are in the gate region and serve to reduce an effective width of the channel in the gate region without substantially reducing the effective width of the channel in the channel access regions.

### Claim 2 (depends on 1)

The method of claim 1, wherein the gate contacts a surface of the isolation regions.

### Claim 3 (depends on 1)

The method of claim 1, wherein each of the isolation regions has a width, and a sum of the widths of the isolation regions is between 20% and 80% a width of the source.

### Claim 4 (depends on 1)

The method of claim 1, wherein each of the isolation regions has a width, and a sum of the widths of the isolation regions is between 10% and 90% the width of the source.

### Claim 5 (depends on 1)

The method of claim 1, wherein the gate is on an N-face of the III-N semiconductor material.

### Claim 6

A method of forming a semiconductor device, comprising:
providing a III-N semiconductor material having a conductive channel therein;
forming a first electrode, a second electrode, and a gate on the III-N semiconductor material, wherein the gate is between the first and second electrodes, and the III-N semiconductor material includes a gate region between the first and second electrodes; and
forming an isolation region in the III-N semiconductor material, the isolation region serving to improve the efficiency of hole collection from the III-N semiconductor material; wherein
the isolation region is a p-type or nominally p-type region; and
the gate is electrically isolated from the isolation region.

### Claim 7 (depends on 6)

The method of claim 6, wherein the device includes a plurality of the isolation regions and a plurality of channel access regions in the III-N semiconductor material, and the isolation regions further serve to reduce an effective width of the conductive channel in the gate region without substantially reducing an effective width of the conductive channel in the channel access regions.

### Claim 8 (depends on 6)

The method of claim 6, wherein the isolation region lies beneath or near the gate.

### Claim 9 (depends on 6)

The method of claim 6, wherein the isolation region lies beneath or near the first electrode.

### Claim 10 (depends on 6)

The method of claim 6, wherein the isolation region lies between the gate and the first electrode.

### Claim 11 (depends on 6)

The method of claim 6, wherein the gate is on an N-face of the III-N semiconductor material.

### Claim 12

A method of forming a transistor device, comprising:
forming a source, a gate, and a drain on a semiconductor material, the semiconductor material having a channel therein, the semiconductor material including a gate region between the source and the drain and a plurality of channel access regions between the source and the gate and between the drain and the gate, respectively; and
forming an isolation region in or near a region of the semiconductor material which has a high electric field or is at a low electric potential during device operation, the isolation region serving to improve the efficiency of hole collection from the semiconductor material, wherein the source contacts a surface of the isolation region.

### Claim 13 (depends on 12)

The method of claim 12, wherein the isolation region lies beneath or near the gate.

### Claim 14 (depends on 12)

The method of claim 12, wherein the isolation region lies between the source and the gate.

### Claim 15 (depends on 12)

The method of claim 12, wherein the isolation region lies between the gate and the drain.

### Claim 16 (depends on 12)

The method of claim 12, further including a field plate which lies over the channel access region between the gate and the drain.

### Claim 17 (depends on 16)

The method of claim 16 wherein the isolation region lies beneath or near to the field plate.

### Claim 18 (depends on 12)

The method of claim 12, wherein the gate contacts a surface of the isolation region.

### Claim 19 (depends on 12)

The method of claim 12, wherein the device is a high-voltage device.

### Claim 20 (depends on 12)

The method of claim 12, wherein the isolation region is capable of collecting holes generated in the semiconductor material.

### Claim 21 (depends on 12)

The method of claim 12, wherein the device is a III-N transistor.

### Claim 22 (depends on 21)

The method of claim 21, wherein the semiconductor material is a III-N material, and the gate is on an N-face of the III-N material.

### Claim 23 (depends on 21)

The method of claim 21, wherein the gate is electrically isolated from the isolation region.

### Claim 24 (depends on 21)

The method of claim 21, wherein the transistor comprises a plurality of isolation regions each having a width, and a sum of the widths of the plurality of isolation regions is between 10% and 90% a width of the source.

### Claim 25 (depends on 24)

The method of claim 24, wherein the sum of the widths of the plurality of isolation regions is between 20% and 80% the width of the source.

### Claim 26

A method of forming a semiconductor device, comprising:
providing a III-N semiconductor material having a conductive channel therein;
forming a first electrode, a second electrode, and a gate, wherein the gate is between the first and second electrodes, and the III-N semiconductor material includes a gate region between the first and second electrodes; and
forming an isolation region in or near a region of the III-N semiconductor material which has a high electric field or is at a low electric potential during device operation, the isolation region serving to improve the efficiency of hole collection from the III-N semiconductor material, wherein the first electrode contacts a surface of the isolation region.

### Claim 27 (depends on 26)

The method of claim 26, wherein the gate is on an N-face of the III-N semiconductor material.

### Claim 28 (depends on 26)

The method of claim 26, wherein the device comprises a plurality of isolation regions each having a width, and a sum of the widths of the plurality of isolation regions is between 10% and 90% a width of the first electrode.

### Claim 29 (depends on 26)

The method of claim 26, wherein the isolation region is capable of collecting holes generated in the III-N semiconductor material.

### Claim 30 (depends on 26)

The method of claim 26, wherein the isolation region is in the gate region, the device includes channel access regions in the semiconductor material that are between the first electrode and the gate and between the second electrode and the gate, respectively, and the isolation region reduces an effective width of the conductive channel in the gate region without substantially reducing the effective width of the channel in the access regions.