# US 9,437,706 B2 · Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processes

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- Number: US 9,437,706 B2
- Document ID: US9437706B2
- Status: Granted
- Kind: B2
- Application number: 14/552,959
- Filed: 2014-11-25
- Published: 2015-03-19
- Granted: 2016-09-06
- Earliest claimed: 2008-12-19
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Niloy Mukherjee; Gilbert Dewey; Matthew V. Metz; Jack T. Kavalieros; Robert S. Chau
- Web page: https://patentgrep.com/patent/US9437706B2

## CPC

- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/165: {Tunnel injectors}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 64/0111: {to Group IV semiconductors}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/42: using a gas or vapour
- H10W 20/076: {in via holes or trenches}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A microelectronic device may be formed with at least one transistor having a source region and a drain region, wherein an interlayer dielectric layer may be formed adjacent the transistor. A trench may be formed through the first interlayer dielectric layer to at least one of the source region and the drain region and a conductive contact may be formed in the trench, wherein the conductive contact comprises a conformal conductive layer separated from the at least one of the source region and the drain region by a conformal insulating layer.

## Claims

### Claim 1

A device, comprising:
a transistor with a source region and a drain region;
an interlayer dielectric layer adjacent the transistor;
a trench through the first interlayer dielectric layer to at least one of the source region and the drain region;
a conductive contact in the trench, the conductive contact being separated from the at least one of the source region and the drain region by a conformal insulating layer, wherein the conductive contact comprises a conformal conductive layer;
a second interlayer dielectric layer;
a first metallization layer adjacent the second interlayer dielectric layer and having a plurality of conductive vias and a plurality of conductive lines;
a third interlayer dielectric layer over the second interlayer dielectric layer;
a second metallization layer adjacent the third interlayer dielectric layer and having a plurality of conductive vias and a plurality of conductive lines; and
wherein at least some of the plurality of conductive vias and the plurality of conductive lines of the first metallization layer and at least some of the plurality of conductive vias and the plurality of conductive lines of the second metallization layer are conductively connected to the conductive contact.

### Claim 2 (depends on 1)

The device of claim 1, wherein the conductive contact further comprises a conductive fill material on the conformal conductive layer and substantially filling the trench.

### Claim 3 (depends on 1)

The device of claim 1, wherein the transistor is a multigate transistor including a fin.

### Claim 4 (depends on 3)

The device of claim 3, wherein the conformal insulating layer is on a top surface and side walls of the fin.

### Claim 5 (depends on 1)

The device of claim 1, wherein the conformal insulating layer has a thickness of about 4 nanometers or less.

### Claim 6 (depends on 1)

The device of claim 1, wherein the conductive contact conformal conductive layer has a thickness of less than 100 nanometers.

### Claim 7 (depends on 1)

The device of claim 1, wherein the transistor is a P-type transistor and the conductive contact comprises a metal with a workfunction above about 5 eV.

### Claim 8 (depends on 1)

The device of claim 1, wherein the transistor is an N-type transistor and the conductive contact comprises a metal with a workfunction below about 3.2 eV.

### Claim 9 (depends on 1)

The device of claim 1, wherein the conductive contact conformal conductive layer comprises aluminum or nickel.

### Claim 10 (depends on 1)

The device of claim 1, wherein the transistor has a channel region that comprises a group III-V material.

### Claim 11 (depends on 1)

The device of claim 1, wherein the conformal insulating layer comprises hafnium oxide.