# US 9,437,705 B2 · Method of manufacturing a spacer for dual gate electronic memory cell and associated electronic memory cell

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,437,705 B2
- Document ID: US9437705B2
- Status: Granted
- Kind: B2
- Application number: 14/341,171
- Filed: 2014-07-25
- Published: 2015-01-29
- Granted: 2016-09-06
- Earliest claimed: 2013-07-26
- Assignees: Commissariat A L'energie Atomique Et Aux Energies Alternatives
- Applicants: Commissariat A L'energie Atomique Et Aux Energies Alternatives
- Inventors: Anthony De Luca; Christelle Charpin-Nicolle
- Web page: https://patentgrep.com/patent/US9437705B2

## CPC

- H10D 64/68: characterised by the insulator, e.g. by the gate insulator
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/691: {having more than two programming levels}
- H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate}
- H10D 64/01: Manufacture or treatment
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 64/516: {the thicknesses being non-uniform}
- H10P 50/263: {of silicon-containing layers}
- H10P 50/268: {of silicon-containing layers}
- H10P 50/283: {by chemical means}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a spacer for an electronic memory including a substrate; a first gate structure; a stack including a plurality of layers whereof at least one of the layers is able to store electric charges, the method including depositing a spacer material layer, at least on the area covered by the stack; ion beam machining the spacer material layer, the ion beam machining being carried out with controlled stopping so as to preserve a residual portion of the thickness of the spacer material layer covering the stack; plasma etching the residual portion of the thickness of the spacer material layer.

## Claims

### Claim 1

A method of manufacturing a spacer for an electronic memory, the electronic memory comprising:
a substrate which extends along a reference plane;
a first gate structure deposited on the substrate, the first gate structure having at least one lateral flank;
a stack comprising a plurality of layers whereof at least one of said layers is able to store electric charges, said stack covering at least the at least one lateral flank of the first gate structure and a portion of the substrate;
said method comprising:
depositing a spacer material layer at least on an area covered by the stack;
ion beam machining the spacer material layer, said ion beam machining being carried out with controlled stopping, so as to preserve a residual portion of the thickness of the spacer material layer covering the stack;
plasma etching the residual portion of the thickness of the spacer material layer, and
following the plasma etching, second plasma etching the stack which is not covered by the spacer material after the plasma etching, said second plasma etching being carried out selectively relative to the spacer material.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the spacer material is doped amorphous silicon or doped polycrystalline silicon.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the ion beam machining is an ion beam machining with Argon.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the ion beam machining is carried out with an incidence of 40°.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the residual portion of the thickness of the spacer material layer has a thickness of between 10 nanometers and 20 nanometers.

### Claim 6 (depends on 5)

The method according to claim 5, wherein the thickness is between 15 nanometers and 20 nanometers.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the deposition of the spacer material layer is carried out over a thickness of between 0.75*e1 and 3*e1, where e1 is the height of the first gate structure.

### Claim 8 (depends on 1)

The method according to claim 1, wherein the second plasma etching is an etching using a fluorine-containing plasma, without Argon and diluted with Helium.

### Claim 9 (depends on 1)

The method according to claim 1, wherein the plasma used during the second plasma etching is a mixture of difluoromethane, of helium and of oxygen, with twice as much helium as oxygen and four times more difluoromethane than oxygen.

### Claim 10 (depends on 1)

A method of manufacturing an electronic memory cell comprising:
a substrate which extends along a reference plane;
a first gate structure deposited on the substrate, the first gate structure having at least one lateral flank;
a stack comprising a plurality of layers whereof at least one of said layers is able to store electric charges, said stack covering at least the at least one lateral flank of the first gate structure and a portion of the substrate;
a second gate structure, insulated from the first gate structure and from the substrate by the stack, the second gate structure being a spacer of the first gate structure;
said method comprising manufacturing the second gate structure, said manufacturing comprising a method for manufacturing a spacer according to claim 1.