# US 9,437,702 B2 · Electronic component manufacturing method and electrode structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,702 B2 - Document ID: US9437702B2 - Status: Granted - Kind: B2 - Application number: 14/327,985 - Filed: 2014-07-10 - Published: 2014-10-30 - Granted: 2016-09-06 - Earliest claimed: 2012-01-24 - Assignees: Canon Anelva Corporation - Applicants: Canon Anelva Corporation - Inventors: Akira Matsuo; Yohsuke Shibuya; Naomu Kitano; Eitaroh Morimoto; Koji Yamazaki; Yu Sato; Takuya Seino - Web page: https://patentgrep.com/patent/US9437702B2 ## CPC - H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)} - C23C 14/046: {Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates} - C23C 14/345: {using substrate bias} - C23C 14/35: by application of a magnetic field, e.g. magnetron sputtering {(C23C14/3457 takes precedence)} - C23C 14/5826: {Treatment with charged particles (C23C14/582 takes precedence)} - C23C 14/586: {Nitriding} - H01J 37/3402: {using supplementary magnetic fields} - H01J 37/3447: {Collimators, shutters, apertures} - H01J 37/3452: {Magnet distribution} - H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)} - H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN} - H10D 84/0177: {the gate conductors having different materials or different implants} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10P 14/412: {Deposition of metallic or metal-silicide materials} - H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10P 14/44: Physical vapour deposition [PVD] - H10W 20/033: {in openings in dielectrics} - H10W 20/048: {by using plasmas or gaseous environments, e.g. by nitriding} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04) - H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract It is an object of the present invention to provide an electronic component manufacturing method, capable of suppressing reduction in a trench opening and suppressing diffusion of a metal film embedded in a trench. An embodiment of the present invention is an electronic component manufacturing method, including the steps of: forming a first electrode constituting layer (e.g., a TiAl film) in a recess (e.g., a trench) formed in a workpiece; forming an ultrathin barrier layer (e.g., a TiAlN film) by forming a nitride layer by plasma-nitriding a surface of the first electrode constituting layer; and forming a second electrode constituting layer (e.g., an Al wiring layer) on the ultrathin barrier layer. ## Claims ### Claim 1 An electronic component manufacturing method, comprising: forming a first electrode constituting layer in a recess formed in a workpiece, the recess having an opening diameter of 15 nm or less; performing plasma nitridation directly on a surface of the first electrode constituting layer; and forming a second electrode constituting layer free of Ti directly contacting the first electrode constituting layer, which has been subjected to the plasma nitridation, wherein in the forming of the first electrode constituting layer, the first electrode constituting layer is formed by sputtering while a magnetic field is formed on a target surface by a magnet unit having a plurality of magnets disposed at grid points of a polygonal grid arranged in a grid, the magnets being disposed such that adjacent magnets have opposite poles, wherein the plasma nitridation is performed while a magnetic field is formed on the target surface by the magnet unit, and wherein in the forming of the second electrode constituting layer, the second electrode constituting layer having a flat surface is formed by sputtering while a magnetic field is formed on the target surface by the magnet unit. ### Claim 2 (depends on 1) The electronic component manufacturing method according to claim 1, wherein the plasma nitridation is performed in an atmosphere of 1 Pa to 200 Pa. ### Claim 3 (depends on 1) The electronic component manufacturing method according to claim 1, further comprising: forming a gate insulating film between the workpiece and the first electrode constituting layer before the forming of the first electrode constituting layer. ### Claim 4 (depends on 3) The electronic component manufacturing method according to claim 3, further comprising: forming a third electrode constituting layer between the first electrode constituting layer and the gate insulating film after the forming of the gate insulating film and before the forming of the first electrode constituting layer. ### Claim 5 (depends on 4) The electronic component manufacturing method according to claim 4, wherein the third electrode constituting layer is a layer to control an operating voltage of the electronic component. ### Claim 6 (depends on 1) The electronic component manufacturing method according to claim 1, wherein the first electrode constituting layer contains Ti and Al, and the second electrode constituting layer contains Al. ### Claim 7 (depends on 1) The electronic component manufacturing method according to claim 1, wherein the forming of the first electrode constituting layer to the forming of the second electrode constituting layer are executed without exposing the workpiece to an atmosphere. ### Claim 8 (depends on 1) The electronic component manufacturing method according to claim 1, wherein in the forming of the first electrode constituting layer, deposition is performed on a bottom of the recess by forming plasma with high density and high ionization rate. ### Claim 9 (depends on 1) The electronic component manufacturing method according to claim 1, wherein in the plasma nitridation, a nitride whose thickness is ultrathin is formed by forming plasma having a suppressed energy. ### Claim 10 (depends on 9) The electronic component manufacturing method according to claim 9, wherein in the plasma nitridation, the plasma having the suppressed energy is formed by reducing a voltage applied to the target to a voltage lower than that in the forming of the first electrode constituting layer. ### Claim 11 (depends on 1) The electronic component manufacturing method according to claim 1, wherein in the forming of the second electrode constituting layer, the second electrode constituting layer having a flat surface is formed by setting the workpiece at a low temperature. ### Claim 12 (depends on 11) The electronic component manufacturing method according to claim 11, wherein the low temperature is from room temperature to 250° C. ### Claim 13 (depends on 1) The electronic component manufacturing method according to claim 1, wherein in the plasma nitridation, a nitride formed directly on the first electrode constituting layer functions as a barrier to suppress diffusion from the second electrode constituting layer. ### Claim 14 (depends on 1) The electronic component manufacturing method according to claim 1, wherein the second electrode constituting layer is formed under a temperature condition at which the second electrode constituting layer does not flow. ### Claim 15 (depends on 1) The electronic component manufacturing method according to claim 1, wherein the second electrode constituting layer includes a low-melting point metal. ### Claim 16 An electrode structure formed by an electronic component manufacturing method comprising: forming a first electrode constituting layer in a recess formed in a workplace, the recess having an opening diameter of 15 nm or less; performing plasma nitridation directly on the surface of the first electrode constituting layer; and forming a second electrode constituting layer free of Ti directly contacting the first electrode constituting layer, which has been subjected to plasma nitridation, wherein the first electrode constituting layer is a layer formed by sputtering while a magnetic field is formed on a target surface by a magnet unit having a plurality of magnets disposed at grid points of a polygonal grid arranged in a grid, the magnets being disposed such that adjacent magnets have opposite poles, wherein the plasma nitridation is performed while a magnetic field is formed on the target surface by the magnet unit, and wherein the second electrode constituting layer is a layer having a flat surface formed by sputtering while a magnetic field is formed on the target surface by the magnet unit.