# US 9,437,701 B2 · Integrated circuit devices with counter-doped conductive gates

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- Number: US 9,437,701 B2
- Document ID: US9437701B2
- Status: Granted
- Kind: B2
- Application number: 14/524,172
- Filed: 2014-10-27
- Published: 2016-04-28
- Granted: 2016-09-06
- Earliest claimed: 2014-10-27
- Assignees: Freescale Semiconductor, Inc.
- Applicants: Weize Chen; Richard J. de Souza; Md M. Hoque; Patrice M. Parris
- Inventors: Weize Chen; Richard J. de Souza; Md M. Hoque; Patrice M. Parris
- Web page: https://patentgrep.com/patent/US9437701B2

## CPC

- H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 64/0131: {the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation}
- H10D 64/01322: {the conductor contacting the insulator having a lateral variation in doping, composition or deposition steps}
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 84/0137: {the gate conductors being silicided}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel. The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.

## Claims

### Claim 1

An integrated circuit device, comprising:
a semiconductor substrate having a substrate surface;
a well of a first conductivity type extending from the substrate surface;
a source of a second conductivity type, which is different from the first conductivity type, formed within the well and extending from the substrate surface;
a drain of the second conductivity type formed within the well and extending from the substrate surface;
a channel formed within the well, the channel extending along the substrate surface and electrically separating the source and the drain;
a conductive gate extending across the substrate surface and along the channel between the source and the drain and comprising
(i) a first gate region of the second conductivity type, wherein the first gate region comprises a second dopant of the second conductivity type,
(ii) a second gate region of the second conductivity type, wherein the second gate region comprises the second dopant of the second conductivity type, and
(iii) a third gate region of the first conductivity type, wherein the third gate region extends between the first gate region and the second gate region, wherein the third gate region comprises a first dopant of the first conductivity type, and further wherein a concentration of the first dopant within the third gate region is at least 110% of a concentration of the second dopant within the first gate region and within the second gate region;
a gate dielectric extending between and electrically isolating the conductive gate and the substrate surface; and
a silicide region in electrical communication with the first gate region, the second gate region, and the third gate region.

### Claim 2 (depends on 1)

The device of claim 1, wherein the first gate region, the second gate region, the third gate region, and the silicide region are formed from a polycrystalline silicon body.

### Claim 3 (depends on 1)

The device of claim 1, wherein the first gate region, the second gate region, and the third gate region extend between the silicide region and the gate dielectric.

### Claim 4 (depends on 1)

The device of claim 1, wherein the third gate region is in direct electrical contact with the first gate region and with the second gate region.

### Claim 5 (depends on 1)

The device of claim 1, wherein the first gate region forms a source-proximal edge of the conductive gate that extends above at least a portion of the source, wherein the second gate region forms a drain-proximal edge of the conductive gate that extends above at least a portion of the drain, and further wherein the third gate region extends across the channel and between the source and the drain.

### Claim 6 (depends on 1)

The device of claim 1, wherein a trench region containing a trench dielectric extends from the substrate surface and around the well to form a portion of a boundary of the well.

### Claim 7 (depends on 1)

The device of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

### Claim 8 (depends on 1)

The device of claim 1, wherein the gate dielectric is formed from a single, continuous layer of dielectric material that extends between the substrate surface and the first gate region, the second gate region, and the third gate region.