# US 9,437,698 B2 · Semiconductor device including a gate structure wrapped around a fin structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,698 B2 - Document ID: US9437698B2 - Status: Granted - Kind: B2 - Application number: 14/476,846 - Filed: 2014-09-04 - Published: 2016-03-10 - Granted: 2016-09-06 - Earliest claimed: 2014-09-04 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Limited - Inventors: Tai-Yuan Wang - Web page: https://patentgrep.com/patent/US9437698B2 ## CPC - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors} - H10D 30/031: {of thin-film transistors [TFT]} - H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 62/121: {oriented parallel to substrates} - H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)} - H10P 50/00: Etching of wafers, substrates or parts of devices - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Methods and structure for a semiconductor device is disclosed, which provides a semiconductor device that includes an integral semiconductor fin structure having a middle section defining a channel region of the semiconductor device. The middle section includes an embedded root portion protruding from an insulating surface on a substrate and a suspended overhead portion arranged above the root portion, which is separated from the overhead portion by a predetermined distance. The root portion and the overhead portion respectively define a substantially identical channel direction. The device further includes a gate structure disposed over the fin structure at the middle section. The gate structure wraps around a cross-section of the overhead portion and caps over the protruded portion of the root portion. ## Claims ### Claim 1 A semiconductor device, comprising: an insulating surface; a fin structure including a root portion arranged above the insulating surface, and an overhead portion arranged above the root portion and separated from the root portion, wherein the root portion and the overhead portion define a cross section that substantially resembles an exclamation mark; and a gate structure wrapping around the overhead portion and the root portion. ### Claim 2 (depends on 1) The device of claim 1, wherein the overhead portion defines a channel region and a source/drain region, the device further comprising an arch structure that separates the channel region from the source/drain region. ### Claim 3 (depends on 1) The device of claim 1, wherein the gate structure includes a gate dielectric layer. ### Claim 4 A semiconductor device, comprising: a fin structure including a root portion, and an overhead portion arranged above the root portion and separated from the root portion; a gate structure wrapping around the overhead portion and including a gate dielectric; and an insulating structure arranged between the root portion and the gate dielectric of the gate structure. ### Claim 5 (depends on 4) The device of claim 4, wherein the overhead portion defines a channel region and a source/drain region, the device further includes an arch structure that separates the channel region from the source/drain region. ### Claim 6 A semiconductor device comprising: a substrate including lower and upper substrate portions; a fin structure formed from the upper substrate portion of the substrate and including a root portion that extends from the lower substrate portion of the substrate, and an overhead portion that is above and separated from the root portion; a gate structure wrapped around the overhead portion of the fin structure; a source/drain region at an end section of the overhead portion of the fin structure; and an arch structure between the gate structure and the source/drain region. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein the gate structure further wraps around the root portion of the fin structure. ### Claim 8 (depends on 6) The semiconductor device of claim 6, further comprising a spacer layer between the root portion of the fin structure and the gate structure. ### Claim 9 (depends on 6) The semiconductor device of claim 6, further comprising an interlayer dielectric between the root portion of the fin structure and the gate structure. ### Claim 10 A semiconductor device comprising: a substrate including lower and upper substrate portions; a fin structure formed from the upper substrate portion of the substrate and including a root portion that extends from the lower substrate portion of the substrate, and an overhead portion that is above and separated from the root portion; a gate structure wrapped around the overhead portion of the fin structure and including a gate dielectric; and a dielectric layer between the root portion of the fin structure and the gate structure and having the same material as the gate dielectric of the gate structure. ### Claim 11 (depends on 6) The semiconductor device of claim 6, wherein the root portion of the fin structure is partially oxidized. ### Claim 12 A semiconductor device comprising: a substrate including lower and upper substrate portions; a fin structure formed from the upper substrate portion of the substrate and including a root portion that extends from the lower substrate portion of the substrate, and an overhead portion that is above and separated from the root portion; a gate structure wrapped around the overhead portion of the fin structure; and an epitaxial layer grown on the overhead portion of the fin structure. ### Claim 13 (depends on 6) The semiconductor device of claim 6, further comprising a shallow trench isolation (STI) feature around the root portion of the fin structure.