# US 9,437,696 B2 · Semiconductor device and method for fabricating the same

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- Number: US 9,437,696 B2
- Document ID: US9437696B2
- Status: Granted
- Kind: B2
- Application number: 14/056,697
- Filed: 2013-10-17
- Published: 2014-12-04
- Granted: 2016-09-06
- Earliest claimed: 2013-05-31
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Ji-In Kim; Do-Youn Kim
- Web page: https://patentgrep.com/patent/US9437696B2

## CPC

- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/00: Isolation regions in semiconductor bodies between components of integrated devices
- H10W 10/01: {Manufacture or treatment}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate having an element isolation region, a trench formed on the element isolation region, a gate electrode buried in the trench, and a plurality of active regions formed on both ends of the gate electrode, wherein a pin is formed under the gate electrode between the active regions.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate including an element isolation region;
a trench formed in the element isolation region;
a gate electrode buried in the trench; and
a plurality of active regions formed under the gate electrode,
wherein the element isolation region has an upper surface and a bottom surface of a fin structure formed under the gate electrode between two adjacent active regions, and
wherein the gate electrode includes a first region and a second region, the first region of the gate electrode is directly contacted to the upper surface of the fin structure included in the element isolation region, and the second region of the gate electrode is directly contacted to the bottom surface of the fin structure included in the element isolation region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the upper surface of the fin structure is higher than a bottom surface of the trench.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the fin structure includes an insulating material.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first region has a first thickness and the second region has a second thickness thicker than the first thickness.

### Claim 5

A semiconductor device, comprising:
a substrate having an element isolation region;
a trench formed in the element isolation region;
a gate electrode buried in the trench; and
a plurality of active regions formed under the gate electrode,
wherein the element isolation region is formed on the gate electrode and includes a fin structure formed under the gate electrode between two adjacent active regions, and
wherein the gate electrode includes a first region and a second region, the first region of the gate electrode is directly contacted to an upper surface of the fin structure included in the element isolation region, and the second region of the gate electrode is directly contacted to a bottom surface of the fin structure included in the element isolation region.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the upper surface of the fin structure is higher than a bottom surface of the trench.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, wherein the first region has a first thickness and the second region has a second thickness thicker than the first thickness.

### Claim 8 (depends on 5)

The semiconductor device of claim 5, wherein the gate electrode includes a metal.

### Claim 9 (depends on 5)

The semiconductor device of claim 5, wherein each of the active regions has a bar shape having a long axis and a short axis, and ends of the long axis of neighboring active regions are adjacent to each other.

### Claim 10

A semiconductor device, comprising:
a substrate having an element isolation region;
a first trench formed in the element isolation region;
a first gate electrode buried in the first trench;
a plurality of active regions formed under the first gate electrode;
a second trench formed in the element isolation region and in parallel to the first trench; and
a second gate electrode buried in the second trench,
wherein the element isolation region is formed under the first gate electrode between two adjacent active regions and includes a fin structure formed protrudedly on a bottom surface of the first trench, and
wherein the first gate electrode includes a first region and a second region, the first region is disposed over an upper surface of the fin structure included in the element isolation region, and the second region is disposed over a bottom surface of the fin structure included in the element isolation region.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the first region of the first gate electrode has a first thickness and the second region of the first gate electrode has a second thickness thicker than the first thickness.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the gate electrode includes a metal.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, wherein each of the active regions has a bar shape having a long axis and a short axis, and ends of the long axis of neighboring active regions are adjacent to each other.

### Claim 14

A semiconductor device, comprising:
a substrate having an element isolation region and an active region defined by the element isolation region;
trenches formed in the active region and the element isolation region; and
a gate electrode buried in the trenches,
wherein the trenches have a same depth in the active region and the element isolation region, and
wherein the element isolation region have a fin structure formed under the gate electrode between two adjacent active regions, and
wherein the gate electrode includes a first region and a second region, the first region of the gate electrode is directly contacted to an upper surface of the fin structure included in the element isolation region, and the second region of the gate electrode is directly contacted to a bottom surface of the fin structure included in the element isolation region.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the bottom surface of the fin structure is formed on a bottom surface of the trench in the element isolation region, and
wherein the upper surface of the fin structure extends protrudedly from the bottom surface of the fin structure.