# US 9,437,694 B1 · Transistor with a low-k sidewall spacer and method of making same

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- Number: US 9,437,694 B1
- Document ID: US9437694B1
- Status: Granted
- Kind: B1
- Application number: 14/676,369
- Filed: 2015-04-01
- Granted: 2016-09-06
- Earliest claimed: 2015-04-01
- Assignees: STMicroelectronics (Crolles 2) SAS
- Applicants: STMicroelectronics (Crolles 2) SAS
- Inventors: Clement Gaumer; Daniel Benoit
- Web page: https://patentgrep.com/patent/US9437694B1

## CPC

- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/514: {characterised by the insulating layers}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/668: {the layer being a silicide, e.g. TiSi2}
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 64/675: {Gate sidewall spacers}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/01: Manufacture or treatment
- H10P 14/43: Chemical deposition, e.g. chemical vapour deposition [CVD]
- H10P 14/44: Physical vapour deposition [PVD]
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A transistor is formed by defining a gate stack on top of a semiconductor layer. The gate stack includes a gate dielectric and a gate electrode. A layer of a first dielectric material, having a first dielectric constant, is deposited on side walls of the gate stack to form sacrificial sidewall spacers. Raised source-drain regions are then epitaxially grown on each side of the gate stack adjacent the sacrificial sidewall spacers. The sacrificial sidewall spacers are then removed to produce openings between each raised source-drain region and the gate stack. A layer of a second dielectric material, having a second dielectric constant less than the first dielectric constant, is then deposited in the openings and on side walls of the gate stack to form low-k sidewall spacers.

## Claims

### Claim 1

A process, comprising:
forming a gate stack on top of a semiconductor layer, said gate stack including a gate dielectric and a gate electrode;
forming a sacrificial sidewall spacer on each side of the gate stack;
epitaxially growing raised source-drain regions on each side of the gate stack adjacent the sacrificial sidewall spacers;
removing the sacrificial sidewall spacers to produce openings between each raised source-drain region and the gate stack; and
filling the openings with a dielectric material having a dielectric constant k<5, wherein the dielectric material having the dielectric constant k<5 is selected from the group consisting of: a silicon oxycarbonitride (SiOCN) material, a silicon carbon oxide (SiCO) material, a silicon carbon nitride (SiCN) and a silicon boron carbon nitride (SiBCN) material.

### Claim 2 (depends on 1)

The process of claim 1, wherein the sacrificial sidewall spacer is formed of a material having a dielectric constant k>5.

### Claim 3 (depends on 1)

The process of claim 1, wherein the sacrificial sidewall spacer is formed of a silicon nitride material.

### Claim 4 (depends on 1)

The process of claim 1, wherein the semiconductor layer is an upper layer of a silicon on insulator (SOI) substrate.

### Claim 5 (depends on 1)

The process of claim 1, further comprising siliciding an upper surface of the gate electrode.

### Claim 6 (depends on 1)

The process of claim 1, further comprising siliciding an upper surface of each raised source-drain region.

### Claim 7 (depends on 1)

The process of claim 1, wherein the gate electrode and raised source-drain regions are portions of a MOSFET.

### Claim 8

A process, comprising:
defining a gate stack on top of a semiconductor layer, said gate stack including a gate dielectric and a gate electrode;
depositing a layer of a first dielectric material having a first dielectric constant on side walls of the gate stack to form sacrificial sidewall spacers;
epitaxially growing raised source-drain regions on each side of the gate stack adjacent the sacrificial sidewall spacers;
removing the sacrificial sidewall spacers to produce openings between each raised source-drain region and the gate stack; and
depositing a layer of a second dielectric material having a second dielectric constant less than the first dielectric constant in said openings and on side walls of the gate stack to form low-k sidewall spacers, wherein the second dielectric material is selected from the group consisting of: silicon oxycarbonitride (SiOCN), silicon carbon oxide (SiCO), silicon carbon nitride (SiCN) and silicon boron carbon nitride (SiBCN).

### Claim 9 (depends on 8)

The process of claim 8, wherein the first dielectric constant is k>5 and the second dielectric constant is k<5.

### Claim 10 (depends on 8)

The process of claim 8, wherein the first dielectric material is silicon nitride.

### Claim 11

A process, comprising:
forming a gate stack on top of a semiconductor layer, said gate stack including a gate dielectric and a gate electrode;
forming a sacrificial sidewall spacer on each side of the gate stack;
epitaxially growing raised source-drain regions on each side of the gate stack adjacent the sacrificial sidewall spacers;
removing the sacrificial sidewall spacers to produce openings between each raised source-drain region and the gate stack; and
filling the openings with a dielectric material selected from the group consisting of: a silicon oxycarbonitride (SiOCN) material, a silicon carbon oxide (SiCO) material, a silicon carbon nitride (SiCN) and a silicon boron carbon nitride (SiBCN) material.

### Claim 12 (depends on 11)

The process of claim 11, wherein the semiconductor layer is an upper layer of a silicon on insulator (SOI) substrate.

### Claim 13 (depends on 11)

The process of claim 11, further comprising siliciding an upper surface of the gate electrode.

### Claim 14 (depends on 11)

The process of claim 11, further comprising siliciding an upper surface of each raised source-drain region.

### Claim 15 (depends on 11)

The process of claim 11, wherein the gate electrode and raised source-drain regions are portions of a MOSFET.