# US 9,437,691 B2 · Column IV transistors for PMOS integration

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- Number: US 9,437,691 B2
- Document ID: US9437691B2
- Status: Granted
- Kind: B2
- Application number: 13/990,249
- Filed: 2011-12-20
- Published: 2013-10-10
- Granted: 2016-09-06
- Earliest claimed: 2010-12-21
- Assignees: Intel Corporation
- Applicants: Glenn A. Glass; Anand S. Murthy
- Inventors: Glenn A. Glass; Anand S. Murthy
- Web page: https://patentgrep.com/patent/US9437691B2

## CPC

- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/4738: {having multiple donor layers}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 48/032: {of unipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunneling transistors [RTT], bulk barrier transistors [BBT], planar doped barrier transistors [PDBT] or charge injection transistors [CHINT]}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/153: {Impurity concentrations or distributions}
- H10D 62/60: Impurity distributions or concentrations
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 62/834: further characterised by the dopants
- H10D 64/0111: {to Group IV semiconductors}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/0113: {the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/853: {comprising FinFETs}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 32/30: Diffusion for doping of conductive or resistive layers
- H10W 20/033: {in openings in dielectrics}
- H10W 20/0526: {by thermal treatment thereof}
- H10W 20/0698: {Local interconnections}
- H10W 20/076: {in via holes or trenches}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each include a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.

## Claims

### Claim 1

A transistor device, comprising:
a substrate having a silicon channel region;
a gate electrode above the silicon channel region; and
source and drain regions formed on or in the substrate and adjacent to the silicon channel region, wherein each of the source and drain regions:
extends above a height of the silicon channel region;
includes a tip region that extends under the gate electrode; and
has a total thickness comprising:
a p-type liner of silicon or germanium or silicon germanium; and
a p-type cap having a germanium concentration in excess of 80 atomic %, wherein the liner is less than 50% of the total thickness and lines the tip region extending under the gate electrode.

### Claim 2 (depends on 1)

The device of claim 1 wherein the device is one of a planar, FinFET, or nanowire PMOS transistor.

### Claim 3 (depends on 1)

The device of claim 1 further comprising metal-germanide source and drain contacts.

### Claim 4 (depends on 1)

The device of claim 1 wherein the thickness ratio of liner thickness to cap thickness is 2:5, or less.

### Claim 5 (depends on 1)

The device of claim 1 wherein the thickness ratio of liner thickness to cap thickness is 1:5, or less.

### Claim 6 (depends on 1)

The device of claim 1 wherein each of the liners has a thickness in the range of about one monolayer to 10 nm, and each of the caps has a thickness in the range of about 50 nm to 500 nm.

### Claim 7 (depends on 1)

The device of claim 1 wherein at least one of the liners and caps has at least one of a graded concentration of germanium and p-type dopant.

### Claim 8 (depends on 7)

The device of claim 7 wherein at least one of the liners has a germanium concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 50 atomic %.

### Claim 9 (depends on 8)

The device of claim 8 wherein the high concentration is in excess of 90 atomic %.

### Claim 10 (depends on 7)

The device of claim 7 wherein at least one of the liners has a p-type dopant concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 1E20 cm−3.

### Claim 11 (depends on 10)

The device of claim 10 wherein the p-dopant of the one or more liners is boron.

### Claim 12 (depends on 7)

The device of claim 7 wherein at least one of the caps has a germanium concentration in excess of 95 atomic %.

### Claim 13 (depends on 7)

The device of claim 7 wherein at least one of the caps has a germanium concentration that is graded from a base level concentration compatible with the corresponding liner to a high concentration in excess of 80 atomic %.

### Claim 14 (depends on 7)

The device of claim 7 wherein at least one of the caps has a p-type dopant concentration that is graded from a base level concentration compatible with the corresponding liner to a high concentration in excess of 1E20 cm−3.

### Claim 15 (depends on 14)

The device of claim 14 wherein the p-dopant of the one or more caps is boron.

### Claim 16 (depends on 1)

The device of claim 1 wherein at least one of the caps further comprises tin.

### Claim 17 (depends on 1)

The device of claim 1 wherein the caps are free of misfit dislocations, threading dislocations, and twins.

### Claim 18 (depends on 1)

An electronic device comprising:
a printed circuit board having an integrated circuit including one or more transistor devices as defined in claim 1.

### Claim 19 (depends on 18)

The electronic device of claim 18 wherein the integrated circuit comprises at least one of a communication chip and a processor.

### Claim 20 (depends on 18)

The electronic device of claim 18 wherein the electronic device is a computing device.

### Claim 21 (depends on 1)

An integrated circuit, comprising:
the device of claim 1, wherein the liner is less than 40% of the total thickness; and
metal-germanide source and drain contacts;
wherein at least one of the thickness ratio of liner thickness to cap thickness is 1:5 or less, and at least one of the caps further comprises tin.

### Claim 22

A method for forming a transistor device, comprising:
providing a substrate having a silicon channel region;
providing a gate electrode above the silicon channel region; and
providing source and drain regions formed on or in the substrate and adjacent to the silicon channel region, wherein each of the source and drain regions:
extends above a height of the silicon channel region;
includes a tip region that extends under the gate electrode; and
has a total thickness comprising:
a p-type liner of silicon or germanium or silicon germanium; and
a p-type cap having a germanium concentration in excess of 80 atomic %, wherein the liner is less than 50% of the total thickness and lines the tip region extending under the gate electrode.

### Claim 23

A transistor device, comprising:
a silicon-containing substrate having a channel region;
a gate electrode above the channel region; and
source and drain regions formed on or in the substrate and adjacent to the channel region, wherein each of the source and drain regions:
extends above a height of the channel region;
includes a tip region that extends under the gate electrode; and
has a total thickness comprising:
a p-type liner of silicon or silicon germanium; and
a p-type cap having a germanium concentration in excess of 80 atomic %, wherein the liner is less than 50% of the total thickness and lines the tip region extending under the gate electrode.

### Claim 24

A transistor device, comprising:
a germanium substrate having a channel region;
a gate electrode above the channel region; and
source and drain regions formed on or in the substrate and adjacent to the channel region, wherein each of the source and drain regions:
extends above a height of the channel region;
includes a tip region that extends under the gate electrode; and
has a total thickness comprising:
a p-type liner of germanium; and
a p-type cap having a germanium concentration in excess of 80 atomic %, wherein the liner is less than 50% of the total thickness and lines the tip region extending under the gate electrode.

### Claim 25 (depends on 24)

The device of claim 24 wherein each liner is included in the composition of the corresponding cap.