# US 9,437,688 B2 · High-quality GaN high-voltage HFETs on silicon

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,437,688 B2
- Document ID: US9437688B2
- Status: Granted
- Kind: B2
- Application number: 14/834,192
- Filed: 2015-08-24
- Published: 2015-12-17
- Granted: 2016-09-06
- Earliest claimed: 2011-12-09
- Assignees: Power Integrations, Inc.
- Applicants: Power Integrations, Inc.
- Inventors: Jamal Ramdani; John P. Edwards; Linlin Liu
- Web page: https://patentgrep.com/patent/US9437688B2

## CPC

- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/357: {of FETs}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/272: {using mask materials other than SiO2 or SiN}
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/3216: {Nitrides}
- H10P 14/3238: {being insulating materials}
- H10P 14/3416: {Nitrides}
- H10P 14/6326: {Deposition processes}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A GaN HFET includes a silicon substrate with an Al2O3 layer above the silicon substrate. The Al2O3 layer has voids formed therein. A plurality of alternating GaN and AlN layers are above the Al2O3 layer. The GaN and AlN layers are under continuous compressive stress.

## Claims

### Claim 1

A GaN HFET, comprising:
a silicon substrate;
an Al2O3 layer above the silicon substrate, the Al2O3 layer having voids formed therein; and
a plurality of alternating GaN and AlN layers above the Al2O3 layer, wherein the GaN and AlN layers are under continuous compressive stress.

### Claim 2 (depends on 1)

The GaN HFET of claim 1, further comprising an amorphous layer located between the silicon substrate and the Al2O3 layer.

### Claim 3 (depends on 1)

The GaN HFET of claim 1, wherein the GaN layers in the plurality of alternating GaN and AlN layers have a minimum thickness of 500 nm.

### Claim 4 (depends on 1)

The GaN HFET of claim 1, wherein the GaN layers in the plurality of alternating GaN and AlN layers have a maximum thickness of 50,000 nm.

### Claim 5

A method of making a GaN HFET comprising:
forming an amorphous film of AlSiO between a silicon wafer and an Al2O3 film on a surface of the silicon wafer; and
depositing a plurality of alternating GaN and AlN layers above the Al2O3 layer.

### Claim 6 (depends on 5)

The method of claim 5, further comprising forming voids in the Al2O3 film on a top surface of a silicon wafer, wherein the top surface of the silicon wafer is along a <111> silicon crystal orientation, and wherein the voids are filled with AlN and GaN.

### Claim 7 (depends on 6)

The method of claim 6, wherein said forming the voids includes exposing portions of the amorphous film of AlSiO along a bottom of the voids.