# US 9,437,683 B2 · Method and structure for FinFET device

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- Number: US 9,437,683 B2
- Document ID: US9437683B2
- Status: Granted
- Kind: B2
- Application number: 14/959,821
- Filed: 2015-12-04
- Published: 2016-03-24
- Granted: 2016-09-06
- Earliest claimed: 2014-04-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Kuo-Cheng Ching; Ka-Hing Fung; Chih-Sheng Chang; Zhiqiang Wu
- Web page: https://patentgrep.com/patent/US9437683B2

## CPC

- H10D 84/853: {comprising FinFETs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0241: {doping of vertical sidewalls, e.g. using tilted or multi-angled implants}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 62/834: further characterised by the dopants
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 14/6309: {of silicon in uncombined form, i.e. pure silicon}
- H10P 14/6322: {Formation by thermal treatments (formation by plasma treatment H10P14/6319)}
- H10P 50/28: of insulating materials
- H10P 50/642: {Chemical etching}
- H10P 50/73: {using masks for insulating materials}
- H10D 62/121: {oriented parallel to substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with source/drain (S/D) features and a high-k/metal gate (HK/MG). A first HK/MG in a first gate region wraps over an upper portion of a first fin structure, the first fin structure including an epitaxial silicon (Si) layer as its upper portion and an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion, and the substrate as its bottom portion. A second HK/MG in a second gate region, wraps over an upper portion of a second fin structure, the second fin structure including an epitaxial SiGe layer as its upper portion, an epitaxial Si layer as it upper middle portion, an epitaxial SiGe layer as its lower middle portion, and the substrate as its bottom portion.

## Claims

### Claim 1

A fin-like field-effect transistor (FinFET) device comprising:
a substrate having a fin-like field-effect transistor (FET) region;
first source/drain (S/D) regions, separated by a first gate region in the FET region;
a first high-k/metal gate (HK/MG) in the first gate region, including wrapping over an upper portion of a first fin structure, the first fin structure including:
an epitaxial silicon (Si) layer as its upper portion;
an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion; and
the substrate as its bottom portion; and
a first S/D feature on top of the first fin structure, having a recessed Si layer, in the first S/D region, the first S/D feature including: a Si:C layer as its lower portion; and a Si:P layer as its upper portion.

### Claim 2 (depends on 1)

The device of claim 1, wherein the FET region is doped n-type (NFET region), and wherein the first fin structures includes:
a first semiconductor material layer epitaxially grown over the substrate; and
a second semiconductor material layer epitaxially grown on top of the first semiconductor material layer;
wherein the second and the first semiconductor material layers form the first fin structure; and
wherein the second semiconductor material layer is the upper portion of the first fin structure, the first semiconductor material layer is the middle portion of the first fin structure and the substrate is a bottom portion of the first fin structure.

### Claim 3 (depends on 2)

The device of claim 2, wherein the first HK/MG wraps over the second semiconductor material layer of the first fin structure.

### Claim 4 (depends on 2)

The device of claim 2, wherein the first S/D features includes:
the first semiconductor S/D feature epitaxially grown on top of a recess in the second semiconductor material layer.

### Claim 5 (depends on 4)

The device of claim 4, wherein the first semiconductor S/D feature includes a lower portion including a first dopant, and an upper portion including a second dopant, different from the first dopant.

### Claim 6 (depends on 2)

The device of claim 2, further comprising:
a dielectric isolation layer between the first fin structures in the NFET region and a second fin structures in a second region.

### Claim 7

A fin-like field-effect transistor (FinFET) device comprising:
a substrate having a fin-like field-effect transistor (FET) region;
source/drain (S/D) regions, separated by a gate region in the FET region;
a HK/MG in the gate region, including wrapping over an upper portion of a first fin structure, the first fin structure including:
an epitaxial SiGe layer as its upper portion;
an epitaxial Si layer as it upper middle portion;
an epitaxial SiGe layer as its lower middle portion; and
the substrate as its bottom portion; and
SiGeB S/D features on top of the first fin structure, having a recessed SiGe layer, in a first S/D region.

### Claim 8 (depends on 7)

The device of claim 7, wherein the FET region is doped p-type (PFET region), and wherein the first fin structures includes a first semiconductor material layer on top of the recessed SiGe layer.

### Claim 9 (depends on 8)

The device of claim 8, wherein the HK/MG wraps over the recessed SiGe layer of the first fin structure.

### Claim 10 (depends on 8)

The device of claim 8, wherein forming the S/D features are epitaxially grown on top of the recessed SiGe layer.

### Claim 11 (depends on 10)

The device of claim 10, wherein the SiGeB S/D features are doped with a first dopant.

### Claim 12

A fin-like field-effect transistor (FinFET) device comprising:
a substrate having an n-type fin-like field-effect transistor (NFET) region and a p-type fin-like field-effect transistor (PFET) region;
first source/drain (S/D) regions, separated by a first gate region in the NFET region;
second source/drain (S/D) regions, separated by a second gate region in the NFET region;
a first high-k/metal gate (HK/MG) in the first gate region, including wrapping over an upper portion of a first fin structure, the first fin structure including:
an epitaxial silicon (Si) layer as its upper portion;
an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion; and
the substrate as its bottom portion;
a second HK/MG in the second gate region, including wrapping over an upper portion of a second fin structure, the second fin structure including:
an epitaxial SiGe layer as its upper portion;
an epitaxial Si layer as it upper middle portion;
an epitaxial SiGe layer as its lower middle portion; and
the substrate as its bottom portion;
a first S/D feature on top of the first fin structure, having a recessed Si layer, in the first S/D region, the first S/D feature including:
a Si:C layer as its lower portion; and
a Si:P layer as its upper portion; and
a SiGeB S/D features on top of the second fin structure, having a recessed SiGe layer, in the second S/D region.

### Claim 13 (depends on 12)

The device of claim 12, wherein:
the upper portion of the first fin structure, the Si layer, has a width in a range of about 4 nm to about 10 nm and a thickness in a range of about 20 nm to about 40 nm;
the middle portion of the first fin structure, the SiGe layer, has a thickness in a range of about 20 nm to about 90 nm and a Ge composition (in atomic percent) in a range of about 30% to about 80%;
the SiGeO feature has a thickness in a range of about 3 nm to about 10 nm;
the upper portion of the second fin structure, the SiGe layer, has a thickness in a range of about 20 nm to about 40 nm and a Ge composition (in atomic percent) in a range of about 45% to about 100%;
a remaining thickness of the recessed Si layer in the first fin structure is in a range of about 3 nm to about 10 nm;
the Si:C layer has a thickness in a range of about 5 nm to about 15 nm and a C composition (in atomic percent) in a range of about 0.5% to about 1.5%;
the Si:P layer has a thickness in a range of about 20 nm to about 35 nm;
a remaining thickness of the recessed SiGe layer in the second fin structure is in a range of about 3 nm to about 10 nm; and
the SiGeB layer has a thickness in a range of about 20 nm to about 35 nm and a Ge composition (in atomic percent) in a range of about 60% to about 100%.

### Claim 14 (depends on 12)

The device of claim 12, wherein the first fin structures includes:
a first semiconductor material layer epitaxially grown over the substrate; and
a second semiconductor material layer epitaxially grown on top of the first semiconductor material layer;
wherein the second and the first semiconductor material layers form the first fin structure; and
wherein the second semiconductor material layer is the upper portion of the first fin structure, the first semiconductor material layer is the middle portion of the first fin structure and the substrate is a bottom portion of the first fin structure.

### Claim 15 (depends on 12)

The device of claim 12, wherein the second fin structure in the PFET region includes:
a third semiconductor material layer epitaxially grown on top of the recessed second semiconductor material layer.

### Claim 16 (depends on 15)

The device of claim 15, wherein the first HK/MG wraps over the second semiconductor material layer of the first fin structure.

### Claim 17 (depends on 16)

The device of claim 16, wherein the second HK/MG wraps over the third semiconductor material layer of the second fin structure.

### Claim 18 (depends on 12)

The device of claim 12, wherein forming the first S/D features includes the first S/D feature epitaxially grown on top of a recess in the second semiconductor material layer.

### Claim 19 (depends on 18)

The device of claim 18, further comprising:
a first dopant in a lower portion of the first S/D feature; and
a second dopant in an upper portion of the first S/D feature;
wherein the first and second dopants are different.

### Claim 20 (depends on 19)

The device of claim 19, wherein the second S/D feature includes a third dopant different from the first and second dopants.