# US 9,437,682 B2 · Semiconductor device and semiconductor device manufacturing method

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- Number: US 9,437,682 B2
- Document ID: US9437682B2
- Status: Granted
- Kind: B2
- Application number: 14/607,154
- Filed: 2015-01-28
- Published: 2015-05-21
- Granted: 2016-09-06
- Earliest claimed: 2009-03-30
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Kabushiki Kaisha Toshiba
- Inventors: Hiroshi Kono; Takashi Shinohe; Makoto Mizukami
- Web page: https://patentgrep.com/patent/US9437682B2

## CPC

- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 12/01: Manufacture or treatment
- H10D 12/031: {of IGBTs}
- H10D 12/411: {Insulated-gate bipolar transistors [IGBT]}
- H10D 12/461: {having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/8325: {Silicon carbide}
- H10D 64/0115: {to silicon carbide}
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 30/22: using masks
- H10D 64/516: {the thicknesses being non-uniform}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The invention provides an ultra-low-on-resistance, excellent-reliability semiconductor device that can finely be processed using SiC and a semiconductor device producing method. A semiconductor device includes: a silicon carbide substrate; a first-conductive-type first silicon carbide layer provided on a first principal surface of the silicon carbide substrate; a second-conductive-type first silicon carbide region formed at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region formed at a surface of the first silicon carbide region; a second-conductive-type third silicon carbide region formed below the second silicon carbide region; a trench piercing through the second silicon carbide region to reach the third silicon carbide region; a gate insulating film; a gate electrode; an interlayer insulating film with which the gate electrode is covered; a first electrode that is formed on the second silicon carbide region and the interlayer insulating film in a side surface of the trench while containing a metallic element selected from a group consisting of Ni, Ti, Ta, Mo, and W; a second electrode that is formed on the third silicon carbide region in a bottom portion of the trench and the first electrode while containing Al; a first main electrode formed on the second electrode; and a second main electrode formed on a second principal surface of the silicon carbide substrate.

## Claims

### Claim 1

A semiconductor device manufacturing method comprising:
forming a first-conductive-type first silicon carbide layer on a first principal surface of a silicon carbide substrate;
forming a first ion implantation mask on an upper surface of the first silicon carbide layer;
forming a first silicon carbide region by ion-implanting a second-conductive-type impurity in the first silicon carbide layer using the first ion implantation mask;
forming a second ion implantation mask on an upper surface of the first silicon carbide layer;
forming a second silicon carbide region by ion-implanting a first-conductive-type impurity in the first silicon carbide layer using the second ion implantation mask;
forming a third silicon carbide region by ion-implanting the second-conductive-type impurity in the first silicon carbide layer using the second ion implantation mask;
forming continuously a gate insulating film on surfaces of the second silicon carbide region, the first silicon carbide region, and the first silicon carbide layer;
forming a gate electrode on the gate insulating film;
forming an interlayer insulating film on the gate electrode;
forming a trench piercing through the second silicon carbide region to reach the third silicon carbide region;
forming a first electrode on the second silicon carbide region on a side surface of the trench while the first electrode contains a metallic element selected from a group consisting of Ni, Ti, Ta, Mo, and W;
forming a second electrode on the third silicon carbide region in a bottom portion of the trench while the second electrode contains Al;
forming a first main electrode on the second electrode; and
forming a second main electrode on a second principal surface of the silicon carbide substrate.

### Claim 2 (depends on 1)

The semiconductor device manufacturing method according to claim 1, wherein the interlayer insulating film is a silicon oxide film.

### Claim 3 (depends on 2)

The semiconductor device manufacturing method according to claim 2, wherein a sidewall insulating film formed by a silicon nitride film is sandwiched between the interlayer insulating film and the first electrode.

### Claim 4 (depends on 1)

The semiconductor device manufacturing method according to claim 1, wherein the silicon carbide substrate is the first conductive type and the device is a MOSFET.

### Claim 5 (depends on 1)

The semiconductor device manufacturing method according to claim 1, wherein the silicon carbide substrate is the second conductive type and the device is a IGBT.