# US 9,437,681 B2 · Dual channel FinFET CMOS device with common strain-relaxed buffer and method for manufacturing thereof

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- Number: US 9,437,681 B2
- Document ID: US9437681B2
- Status: Granted
- Kind: B2
- Application number: 14/709,696
- Filed: 2015-05-12
- Published: 2016-01-28
- Granted: 2016-09-06
- Earliest claimed: 2014-07-25
- Assignees: Imec Vzw; Samsung Electronics Co., Ltd.
- Applicants: Imec Vzw; Samsung Electronics Co. Ltd.
- Inventors: Seung Hun Lee; Geert Eneman
- Web page: https://patentgrep.com/patent/US9437681B2

## CPC

- H10D 30/751: {having composition variations in the channel regions}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 30/798: {being provided in or under the channel regions}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/853: {comprising FinFETs}
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A CMOS semiconductor FinFET device and a method for manufacturing a CMOS semiconductor FinFET device are disclosed. The device may comprise an nFinFET and a pFinFET having a channel region comprising Ge on a common strain-relaxed buffer layer comprising SiGe. The concentration of Ge in the channel regions is higher than the concentration of Ge in the strain-relaxed buffer layer. The device further comprises a source/drain region for the nFinFET, the source/drain region comprising SiGe; and a source/drain region for the pFinFET, the second source/drain region comprising Ge.

## Claims

### Claim 1

A CMOS device comprising
a semiconductor substrate,
a patterned strain-relaxed buffer layer of fins comprising silicon germanium (SiGe) on the semiconductor substrate;
on the patterned strain-relaxed buffer layer, an nFinFET having an n-channel region and a pFinFET having a p-channel region, both channel regions isolated from each other by an isolation region and comprising germanium (Ge) whereby the concentration of Ge in the channel regions is higher than the concentration of Ge in the strain-relaxed buffer layer;
source/drain regions comprising SiGe for the nFinFET; and
source/drain regions comprising Ge for the pFiNFET.

### Claim 2 (depends on 1)

The CMOS device according to claim 1, wherein the concentration of Ge in the strain-relaxed buffer layer is in the range of 25% to 90%.

### Claim 3 (depends on 1)

The CMOS device according to claim 1, wherein the concentration of Ge in the channel region of the nFinFET and of the pFinFET is in the range of 90% to 100%.

### Claim 4 (depends on 1)

The CMOS device according to claim 1, wherein the nFinFET has recessed source/drain regions, and wherein the pFinFET has raised source/drain regions.

### Claim 5 (depends on 1)

The CMOS device according to claim 1, wherein the concentration of Ge in the nFinFET source/drain regions is lower than the concentration of Ge in the strain-relaxed buffer layer.

### Claim 6 (depends on 5)

The CMOS device according to claim 5, wherein the concentration of Ge in the nFinFET source/drain region is less than 80%.

### Claim 7 (depends on 1)

The CMOS device according to claim 1, wherein the concentration of Ge in the pFinFET source/drain regions is higher than the concentration of Ge in the strain-relaxed buffer layer.

### Claim 8 (depends on 7)

The CMOS device according to claim 7, wherein the concentration of Ge in the pFinFET source/drain regions is in the range between 35% and 100%.

### Claim 9 (depends on 1)

The CMOS device according to claim 1, wherein the p-channel region and the n-channel region comprise a same material.

### Claim 10

A method for manufacturing a CMOS device comprising:
providing a semiconductor substrate;
providing a patterned strain-relaxed buffer layer of fins comprising silicon germanium (SiGe) on the semiconductor substrate;
providing on the fins of the patterned strain-relaxed buffer layer an nFinFET and a pFinFET isolated by an isolation region, the nFinFET having an n-channel region and the pFinFET having a p-channel region, whereby both channel regions comprise germanium (Ge) in a concentration higher than the concentration of Ge in the strain-relaxed buffer layer;
providing source/drain regions comprising SiGe for the nFinFET; and
providing source/drain regions comprising Ge for the pFinFET.

### Claim 11 (depends on 10)

The method for manufacturing a CMOS device according to claim 10 wherein providing a patterned strain-relaxed buffer layer comprises:
providing the strain-relaxed buffer layer on the semiconductor substrate;
patterning the strain-relaxed buffer layer thereby forming fins; and
providing a dielectric layer on the patterned strain-relaxed buffer layer.

### Claim 12 (depends on 11)

The method for manufacturing a CMOS device according to claim 11 wherein providing on the fins of the patterned strain-relaxed buffer layer an nFinFET and a pFinFET further comprises:
recessing a top part of the fins of the patterned strain-relaxed buffer layer thereby forming trenches having a reduced depth;
epitaxial growing in the reduced depth trenches on the strain-relaxed buffer layer an upper layer thereby forming the n-channel of the nFinFET and the p-channel of the pFinFET; and
removing a top part of the dielectric layer thereby revealing the n-channel and p-channel.

### Claim 13 (depends on 10)

The method for manufacturing a CMOS device according to claim 10 wherein providing the patterned strain-relaxed buffer layer of fins comprises:
patterning the semiconductor substrate thereby forming semiconductor fins isolated from each other by isolation regions;
recessing the semiconductor material of the semiconductor fins down to the bottom part of the isolation regions thereby forming trenches in between the isolation regions; and
epitaxial growing the strain-relaxed buffer layer in part of the trenches thereby forming fins.

### Claim 14 (depends on 13)

The method for manufacturing a CMOS device according to claim 13 wherein providing on the fins of the patterned strain-relaxed buffer layer the nFinFET and the pFinFET further comprises:
epitaxial growing an upper layer on the epitaxial grown strain-relaxed buffer layer in the remaining part of the trenches thereby forming the n-channel and the p-channel; and
removing a top part of the dielectric layer thereby revealing the n-channel and p-channel.

### Claim 15 (depends on 10)

The method for manufacturing a CMOS device according to claim 10, wherein the concentration of Ge in the strain-relaxed buffer layer is in the range of 25% to 90%.

### Claim 16 (depends on 10)

The method for manufacturing a CMOS device according to claim 10, wherein providing the nFinFET source/drain regions comprises providing recessed source/drain regions, and wherein providing the pFinFET source/drain regions comprises providing raised source/drain regions.

### Claim 17 (depends on 10)

The method for manufacturing a CMOS device according to claim 10, wherein the concentration of Ge in the nFinFET source/drain regions is less than the concentration of Ge in the strain-relaxed buffer layer, and wherein the concentration of Ge in the pFinFET source/drain regions is higher than concentration of Ge in the strain-relaxed buffer layer.

### Claim 18 (depends on 17)

The method for manufacturing a CMOS device according to claim 17, wherein the concentration of Ge in the nFinFET source/drain regions is in the range between 35% and 100%, and wherein the concentration of Ge in the pFinFET source/drain regions is less than 80%.

### Claim 19 (depends on 10)

The method for manufacturing a CMOS device according to claim 10, wherein the n-channel region and the p-channel region comprise a same material.