# US 9,437,680 B1 · Silicon-on-insulator substrates having selectively formed strained and relaxed device regions

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,437,680 B1
- Document ID: US9437680B1
- Status: Granted
- Kind: B1
- Application number: 14/674,086
- Filed: 2015-03-31
- Granted: 2016-09-06
- Earliest claimed: 2015-03-31
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Bruce B. Doris; Ali Khakifirooz; Devendra K. Sadana
- Web page: https://patentgrep.com/patent/US9437680B1

## CPC

- H10D 30/751: {having composition variations in the channel regions}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 30/796: {having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 86/01: Manufacture or treatment
- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/2925: {Surface structures}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/38: {characterised by treatments done after the formation of the materials}
- H10P 90/1916: {with separation or delamination along an ion implanted layer, e.g. Smart-cut}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 15/00: Highly-doped buried regions of integrated devices
- H10W 15/01: {Manufacture or treatment}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a semiconductor device substrate includes forming a donor wafer having a surface comprising regions of relaxed silicon and regions of relaxed silicon germanium (SiGe); epitaxially growing a silicon device layer on the surface of the donor wafer, wherein the silicon device layer comprises tensile strained silicon on the regions of relaxed silicon germanium of the donor wafer, and wherein the silicon device layer comprises relaxed silicon on the regions of relaxed silicon of the donor wafer; and transferring the silicon device layer from the donor wafer to a handle wafer comprising a bulk substrate and an insulator layer, so as to form a silicon-on-insulator (SOI) substrate with the silicon device layer maintaining regions of tensile strained silicon and regions of relaxed silicon.

## Claims

### Claim 1

A semiconductor device substrate, comprising:
a bulk layer;
an oxide layer formed on the bulk layer;
a donor wafer comprising a plurality of regions of relaxed SiGe layer, and a plurality of regions of relaxed silicon layer, formed by epitaxially growing a graded silicon germanium (SiGe) buffer layer directly on a silicon substrate and a relaxed SiGe layer directly on the graded SiGe buffer layer;
forming a patterned hardmask directly on the relaxed SiGe layer;
removing selective portions of the graded SiGe buffer layer and the relaxed SiGe layer; epitaxially growing the plurality of regions of relaxed silicon layer directly on the silicon substrate, corresponding to the removed selective portions of the graded SiGe buffer layer and the relaxed SiGe layer; and removing the hardmask layer; and a silicon device layer comprising a plurality of regions of tensile strained silicon layer on the plurality of regions of relaxed SiGe layer of the donor wafer, and a plurality of regions of additional relaxed silicon layer on the plurality of regions of relaxed silicon layer of the donor wafer, formed by:
epitaxially growing the silicon device layer directly on the surface of the donor wafer; and transferring the silicon device layer from the donor wafer to a handle wafer comprising a bulk substrate and an insulator layer, so as to form a silicon-on-insulator (SOI) substrate with the silicon device layer maintaining the plurality of regions of tensile strained silicon and the plurality of regions of relaxed silicon.

### Claim 2 (depends on 1)

The substrate of claim 1, further comprising a spacer over side walls of regions corresponding to the removed selective portions of the graded SiGe buffer layer and the relaxed SiGe layer, wherein the spacer comprises SiN and SiO2.

### Claim 3

A semiconductor device donor wafer, comprising: a donor substrate formed by epitaxially growing a compressively strained SiGe layer directly on the donor substrate and implanting a defect layer in the compressively strained SiGe layer which relaxes an upper portion of the compressively strained SiGe layer above the defect layer; forming a patterned hardmask directly on the relaxed SiGe layer; removing selective portions of the compressively strained SiGe layer and the relaxed SiGe layer; epitaxially growing additional relaxed silicon layer directly on the donor substrate, corresponding to the removed selective portions of the compressively strained SiGe layer and the relaxed SiGe layer; and
removing the hardmask layer to form a donor wafer comprising a plurality of regions of relaxed SiGe layer, and a plurality of regions of additional relaxed silicon layer; and a silicon device layer epitaxially grown on the surface of the donor wafer and transferred from the donor wafer to a handle wafer comprising a bulk substrate and an insulator layer, so as to form a silicon-on-insulator (SOI) substrate with the silicon device layer maintaining the plurality of regions of tensile strained silicon layer on the plurality of regions of relaxed SiGe layer of the donor wafer, and the plurality of regions of relaxed silicon layer on the plurality of regions of additional relaxed silicon layer of the donor wafer.

### Claim 4 (depends on 3)

The semiconductor device donor wafer of claim 3, wherein the donor wafer comprises regions of relaxed silicon germanium and regions of relaxed silicon, such that the first regions of relaxed silicon of the silicon device layer are disposed on the regions of additional relaxed silicon of the donor wafer, and the second regions of tensile strained silicon are disposed on the regions of relaxed silicon germanium of the donor wafer.

### Claim 5 (depends on 4)

The semiconductor device donor wafer of claim 4, wherein the compressively strained SiGe layer is grown to a thickness of about 200-600 nanometers (nm).

### Claim 6 (depends on 4)

The semiconductor device donor wafer of claim 4, wherein bottom surfaces of the regions of relaxed silicon germanium of the donor wafer abut a buried oxide layer of the donor wafer.

### Claim 7 (depends on 4)

The semiconductor device donor wafer of claim 4, further comprising a hydrogen implanted bubble layer formed below a bottom surface of the silicon device layer.