# US 9,437,679 B2 · Semi-conductor device with epitaxial source/drain facetting provided at the gate edge > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,679 B2 - Document ID: US9437679B2 - Status: Granted - Kind: B2 - Application number: 14/533,154 - Filed: 2014-11-05 - Published: 2015-03-05 - Granted: 2016-09-06 - Earliest claimed: 2012-06-27 - Assignees: Globalfoundries Inc. - Applicants: International Business Machines Corporation - Inventors: Thomas N. Adam; Kangguo Cheng; Bruce B. Doris; Ali Khakifirooz; Alexander Reznicek - Web page: https://patentgrep.com/patent/US9437679B2 ## CPC - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions} - H10D 84/0128: {Manufacturing their channels} - H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions} - H10D 84/0151: {Manufacturing their isolation regions} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 86/01: Manufacture or treatment - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor structure includes an active layer located on a substrate and a first and a second gate structure located on the active layer. A first raised epitaxial region is located on the active layer between the first and the second gate. The first raised epitaxial region has a first facet shaped edge and a first vertical shape edge, such that the first facet shaped edge is located adjacent the first gate structure. A second raised epitaxial region is also located on the active layer between the first and the second gate structure. The second raised epitaxial region has a second facet shaped edge and a second vertical shape edge, such that the second facet shaped edge is located adjacent the second gate structure. A trench region is located between the first and the second vertical shaped edge for electrically isolating the first and the second raised epitaxial region. ## Claims ### Claim 1 A semiconductor structure comprising: a substrate; an isolation layer on the substrate; an active layer on the isolation layer; a first gate structure and a second gate structure located on the active layer; a raised epitaxial layer on the active layer between the first gate structure and the second gate structure; a trench extending vertically through the raised epitaxial layer and the active layer such that the trench has a bottom comprising a portion of the isolation layer and such that the raised epitaxial layer comprises: a first raised epitaxial region located on the active layer between the first gate structure and the trench, the first raised epitaxial region having a first facet shaped edge adjacent to the first gate structure and a first vertical shaped edge opposite the first facet shaped edge; and, a second raised epitaxial region located on the active layer between the trench and the second gate structure, the second raised epitaxial region having a second facet shaped edge adjacent to the second gate structure and a second vertical shaped edge opposite the second facet shaped edge; and, trench sidewall spacers within the trench and comprising: a first trench sidewall spacer on the portion of the isolation layer at the bottom of the trench and positioned laterally immediately adjacent to a first sidewall of the trench so as to be positioned laterally immediately adjacent to the active layer and the first vertical shaped edge of the first raised epitaxial region; and, a second trench sidewall spacer on the portion of the isolation layer at the bottom of the trench and positioned laterally immediately adjacent to a second sidewall of the trench opposite the first sidewall so as to be positioned laterally immediately adjacent to the active layer and the second vertical shaped edge of the second raised epitaxial region, the trench sidewall spacers comprising remaining vertical portions of a deposited and etched dielectric layer. ### Claim 2 (depends on 1) The semiconductor structure of claim 1, the first raised epitaxial region corresponding to a first transistor device and the second raised epitaxial region corresponding to a second transistor device. ### Claim 3 (depends on 1) The semiconductor structure of claim 1, the active layer comprising an extremely thin silicon-on-insulator layer. ### Claim 4 (depends on 1) The semiconductor structure of claim 1, further comprising: first gate sidewall spacers located on opposing sidewalls of both the first gate structure and the second gate structure; and, second gate sidewall spacers located on the first gate sidewall spacers, the second gate sidewall spacers filling spaces between the first gate sidewall spacers and the first facet shaped edge of the first raised epitaxial region adjacent to the first gate structure and the second facet shaped edge of the second raised epitaxial region adjacent to the second gate structure. ### Claim 5 (depends on 4) The semiconductor structure of claim 4, the first gate sidewall spacers, the second gate sidewall spacers and the trench sidewall spacers comprising the same dielectric materials. ### Claim 6 (depends on 4) The semiconductor structure of claim 4, the second gate sidewall spacers and the trench sidewall spacers comprising the same dielectric materials. ### Claim 7 (depends on 4) The semiconductor structure of claim 4, further comprising silicide layers on the first raised epitaxial region and the second raised epitaxial region extending between the second gate sidewall spacers and the trench sidewall spacers. ### Claim 8 A semiconductor structure comprising: a substrate; an isolation layer on the substrate; an active layer on the isolation layer; a first gate structure and a second gate structure on the active layer; a raised epitaxial layer on the active layer between the first gate structure and the second gate structure; a trench extending vertically through the raised epitaxial layer and the active layer such that the trench has a bottom comprising a portion of the isolation layer and such that the raised epitaxial layer comprises: a first raised epitaxial region located on the active layer between the first gate structure and the trench, the first raised epitaxial region having a first facet shaped edge adjacent to the first gate structure and a first vertical shaped edge opposite the first facet shaped edge; and, a second raised epitaxial region located on the active layer between the trench and the second gate structure, the second raised epitaxial region having a second facet shaped edge adjacent to the second gate structure and a second vertical shaped edge opposite the second facet shaped edge; silicide layers on the raised epitaxial layer, the silicide layers comprising: a first silicide layer on the first raised epitaxial region; and a second silicide layer on the second raised epitaxial region; and, trench sidewall spacers within the trench and comprising: a first trench sidewall spacer on the portion of the isolation layer at the bottom of the trench and positioned laterally immediately adjacent to a first sidewall of the trench so as to be positioned laterally immediately adjacent to the active layer, the first vertical shaped edge of the first raised epitaxial region, and the first silicide layer; and, a second trench sidewall spacer on the portion of the isolation layer at the bottom of the trench and positioned laterally immediately a second sidewall of the trench opposite the first sidewall so as to be positioned laterally immediately adjacent to the active layer, the second vertical shaped edge of the second raised epitaxial region and the second silicide layer, the trench sidewall spacers comprising remaining vertical portions of a deposited and etched dielectric layer. ### Claim 9 (depends on 8) The semiconductor structure of claim 8, the first raised epitaxial region corresponding to a first transistor device and the second raised epitaxial region corresponding to a second transistor device. ### Claim 10 (depends on 8) The semiconductor structure of claim 8, the active layer comprising an extremely thin silicon-on-insulator layer. ### Claim 11 (depends on 8) The semiconductor structure of claim 8, further comprising: first gate sidewall spacers located on opposing sidewalls of both the first gate structure and the second gate structure; and, second gate sidewall spacers located on the first gate sidewall spacers, the second gate sidewall spacers filling spaces between the first gate sidewall spacers and the first facet shaped edge of the first raised epitaxial region adjacent to the first gate structure and the second facet shaped edge of the second raised epitaxial region adjacent to the second gate structure. ### Claim 12 (depends on 11) The semiconductor structure of claim 11, the first gate sidewall spacers, the second gate sidewall spacers and the trench sidewall spacers comprising the same dielectric materials. ### Claim 13 (depends on 11) The semiconductor structure of claim 11, the second gate sidewall spacers and the trench sidewall spacers comprising the same dielectric materials. ### Claim 14 (depends on 11) The semiconductor structure of claim 11, the silicide layers extending between the second gate sidewall spacers and the trench sidewall spacers. ### Claim 15 A semiconductor structure comprising: an oxide layer; an active layer on the oxide layer; a first gate structure and a second gate structure on the active layer; a raised epitaxial layer on the active layer between the first gate structure and the second gate structure; a trench extending vertically through the raised epitaxial layer and the active layer to the oxide layer such that a bottom of the trench comprises a portion of the oxide layer and such that the raised epitaxial layer comprises: a first raised epitaxial region located on the active layer between the first gate structure and the trench, the first raised epitaxial region having a first facet shaped edge adjacent to the first gate structure and a first vertical shaped edge opposite the first facet shaped edge; and, a second raised epitaxial region located on the active layer between the trench and the second gate structure, the second raised epitaxial region having a second facet shaped edge adjacent to the second gate structure and a second vertical shaped edge opposite the second facet shaped edge; first gate sidewall spacers on opposing sidewalls of both the first gate structure and the second gate structure; second gate sidewall spacers on the first gate sidewall spacers, the second gate sidewall spacers filling spaces between the first gate sidewall spacers and the first facet shaped edge of the first raised epitaxial region adjacent to the first gate structure and the second facet shaped edge of the second raised epitaxial region adjacent to the second gate structure; silicide layers on the raised epitaxial layer, the silicide layers comprising: a first silicide layer on a first top surface only of the first raised epitaxial region; and, a second silicide layer on a second top surface only of the second raised epitaxial region; and, trench sidewall spacers within the trench and comprising: a first trench sidewall spacer on the portion of the oxide layer at the bottom of the trench and positioned laterally immediately adjacent to a first sidewall of the trench so as to be positioned laterally immediately adjacent to the active layer, the first vertical shaped edge of the first raised epitaxial region, and the first silicide layer; and, a second trench sidewall spacer on the portion of the oxide layer at the bottom of the trench and positioned laterally immediately adjacent to a second sidewall of the trench opposite the first sidewall so as to be positioned laterally immediately adjacent to the active layer, the second vertical shaped edge of the second raised epitaxial region and the second silicide layer, the second gate sidewall spacers and the trench sidewall spacers comprising remaining portions of a deposited and etched dielectric layer, the first silicide layer extending laterally between the first trench sidewall spacer and a first one of the second gate sidewall spacers such that a first top surface of the first raised epitaxial region is covered by and immediately adjacent to the first silicide layer only, the first one of the second gate sidewall spacers being on a corresponding first one of the first gate sidewall spacers that is adjacent to the first gate structure, and the second silicide layer extending laterally between the second trench sidewall spacer and a second one of the second gate sidewall spacers such that a second top surface of the second raised epitaxial region is covered by and immediately adjacent to the second silicide layer only, the second one of the second gate sidewall spacers being on a corresponding second one of the first gate sidewall spacers that is adjacent to the second gate structure. ### Claim 16 (depends on 15) The semiconductor structure of claim 15, the first raised epitaxial region corresponding to a first transistor device and the second raised epitaxial region corresponding to a second transistor device. ### Claim 17 (depends on 15) The semiconductor structure of claim 15, the active layer comprising an extremely thin silicon-on-insulator layer. ### Claim 18 (depends on 15) The semiconductor structure of claim 15, the first gate sidewall spacers, the second gate sidewall spacers and the trench sidewall spacers comprising the same dielectric materials. ### Claim 19 (depends on 15) The semiconductor structure of claim 15, the second gate sidewall spacers and the trench sidewall spacers comprising the same dielectric materials.