# US 9,437,678 B2 · Fabrication method of semiconductor device, evaluation method of semiconductor device, and semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,678 B2 - Document ID: US9437678B2 - Status: Granted - Kind: B2 - Application number: 14/674,478 - Filed: 2015-03-31 - Published: 2015-10-29 - Granted: 2016-09-06 - Earliest claimed: 2014-04-23 - Assignees: Fuji Electric Co., Ltd.; Denso Corporation - Applicants: Fuji Electric Co., Ltd.; Denso Corporation - Inventors: Seiji Momota; Hitoshi Abe; Kenji Kouno; Hiromitsu Tanabe - Web page: https://patentgrep.com/patent/US9437678B2 ## CPC - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - G01R 31/2601: {Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence)} - H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs} - H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs} - H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions} - H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates} - H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} - H10D 64/519: {characterised by their top-view geometrical layouts} - H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics} - H10P 74/27: {Structural arrangements therefor} - H10W 72/075: {of bond wires} - H10W 72/07536: {Soldering or alloying} - H10W 72/5453: {connecting between multiple bond pads on a chip, e.g. daisy chain} - H10W 72/5473: {multiple bond wires connected to a common bond pad} - H10W 72/926: {Multiple bond pads having different sizes} - H10W 72/951: {Materials of bond pads} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 90/753: {between laterally-adjacent chips} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A fabrication method of a semiconductor device that includes trench gate structures each having a gate electrode extending in a depth-direction of an element, where first trench gate structures contribute to controlling the element and second trench gate structures do not contribute. The fabrication method includes forming the trench gate structures on a front face of a semiconductor substrate; forming on the front face, an electrode pad connected to the gate electrode of at least one trench gate structure; executing screening by applying a predetermined voltage between the electrode pad and an electrode portion having a potential other than a gate potential, to apply the predetermined voltage to gate insulator films in contact with each gate electrode connected to the electrode pad; and forming the second trench gate structures having the gate electrodes connected to the electrode pad, by short-circuiting the electrode portion to the electrode pad after executing screening. ## Claims ### Claim 1 A fabrication method of a semiconductor device that includes a plurality of trench gate structures each having a gate electrode extending in a depth direction of an element and a gate insulator film, the plurality of trench gate structures including first trench gate structures respectively contributing to control of the element and second trench gate structures respectively not contributing to the control of the element, the fabrication method of a semiconductor device comprising: forming the plurality of trench gate structures on a front face of a semiconductor substrate; forming on the front face of the semiconductor substrate, an electrode pad connected to the gate electrode of at least one of the trench gate structures among the plurality of trench gate structures; executing screening by applying a predetermined voltage to gate insulator films in contact with each gate electrode connected to the electrode pad by applying the predetermined voltage between an electrode portion having a potential other than a gate potential and the electrode pad; and forming the second trench gate structures respectively having the gate electrode connected to the electrode pad, by short-circuiting the electrode portion and the electrode pad to each other after executing screening. ### Claim 2 (depends on 1) The fabrication method of a semiconductor device according to claim 1, wherein the forming of the electrode pad includes forming the electrode pad to which each gate electrode of the plurality of trench gate structures is connected by a single wire, the fabrication method further comprising after executing screening and before forming the second gate structures, electrically separating gate electrodes from the single wire and connecting the separated gate electrodes to a second electrode pad different from the electrode pad, wherein the forming of the second trench gate structures includes forming the second trench gate structures respectively comprising the separated gate electrodes, by short-circuiting to each other the electrode portion and the second electrode pad connected to the separated gate electrodes. ### Claim 3 (depends on 1) The fabrication method of a semiconductor device according to claim 1, wherein the forming of the second trench gate structures includes forming a plated film to cover the electrode portion and the electrode pad to which each gate electrode of the second trench gate structures is connected, and the electrode portion and the electrode pad to which each gate electrode of the second trench gate structures is connected, being connected through the plated film spreading between the electrode portion and the electrode pad to which each gate electrode of the second trench gate structures is connected. ### Claim 4 (depends on 1) The fabrication method of a semiconductor device according to claim 1, wherein the forming of the second trench gate structures includes forming a plated film on a surface of the electrode portion and a surface of the electrode pad to which each gate electrode of the second trench gate structures is connected, and soldering an electrode layer to be an electrode terminal, to the electrode pad to which the electrode portion and each gate electrode of the second trench gate structures are connected through the plated film, and the electrode portion and the electrode pad to which each gate electrode of the second trench gate structures is connected are connected by a solder layer spreading between the electrode portion and the electrode pad to each the gate electrode of the second trench gate structures is connected. ### Claim 5 (depends on 1) The fabrication method of a semiconductor device according to claim 1, wherein the forming of the second trench gate structures includes executing a wiring process using wire bonding, respectively for the electrode portion and each gate electrode of the first trench gate structures, and connecting by the wire bonding, the electrode portion and the electrode pad to which each gate electrode of the second trench structures is connected. ### Claim 6 (depends on 1) The fabrication method of a semiconductor device according to claim 1, further comprising executing after screening and before forming the second gate structures, a wiring process using wire bonding, respectively for the electrode portion and each gate electrode of the first trench gate structures, wherein the forming the second gate structures includes connecting the electrode pad to which each gate electrode of the second trench gate structures is connected and the electrode portion disposed in an external circuit. ### Claim 7 (depends on 1) The fabrication method of a semiconductor device according to claim 1, wherein the electrode portion is an emitter electrode electrically connected to a portion of the semiconductor substrate, the portion being along trenches of the trench gate structures. ### Claim 8 (depends on 1) A semiconductor device fabricated using the fabrication method of a semiconductor device according to claim 1. ### Claim 9 An evaluation method of a semiconductor device that includes a plurality of trench gate structures each having a gate electrode extending in a depth direction of an element and a gate insulator film, the plurality of trench gate structures including first trench gate structures respectively contributing to control of the element and second trench gate structures respectively not contributing to the control of the element, the evaluation method comprising: executing screening before forming the second trench gate structures respectively having the gate electrode connected to an electrode pad by short-circuiting to an electrode portion having a potential other than a gate potential, the electrode pad to which the gate electrode of at least one trench gate structure is connected among the plurality of trench gate structures formed on a front face of a semiconductor substrate, wherein the screening is executed by applying a predetermined voltage to gate insulator films respectively in contact with the gate electrode connected to the electrode pad by applying the predetermined voltage between the electrode portion and the electrode pad.