# US 9,437,677 B2 · Deposition on a nanowire using atomic layer deposition

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- Number: US 9,437,677 B2
- Document ID: US9437677B2
- Status: Granted
- Kind: B2
- Application number: 13/604,739
- Filed: 2012-09-06
- Published: 2012-12-27
- Granted: 2016-09-06
- Earliest claimed: 2011-01-25
- Assignees: Globalfoundries Inc.
- Applicants: Dechao Guo; Zhengwen Li; Kejia Wang; Zhen Zhang; Yu Zhu
- Inventors: Dechao Guo; Zhengwen Li; Kejia Wang; Zhen Zhang; Yu Zhu
- Web page: https://patentgrep.com/patent/US9437677B2

## CPC

- H10D 62/121: {oriented parallel to substrates}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- B82Y 30/00: Nanotechnology for materials or surface science, e.g. nanocomposites
- B82Y 40/00: Manufacture or treatment of nanostructures
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 64/64: Electrodes comprising a Schottky barrier to a semiconductor
- H10D 64/647: {Schottky drain or source electrodes for IGFETs}
- H10D 86/01: Manufacture or treatment
- H10D 86/011: {comprising FinFETs}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 86/215: {comprising FinFETs}
- H10K 10/484: {characterised by the channel regions}
- H10K 10/491: {Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]}
- H10K 10/468: {characterised by the gate dielectrics}
- H10K 85/221: {Carbon nanotubes}
- Y10S 977/762: Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
- Y10S 977/938: Field effect transistors, FETS, with nanowire- or nanotube-channel region
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A semiconductor device includes a substrate, a nanowire, a first structure, and a second structure. The nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate, where the nanowire includes a layer on a surface of the nanowire, where the layer includes at least one of silicide and carbide, where the layer has a substantially uniform shape.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate, a first structure disposed on the substrate, a second structure disposed on the substrate, a first nanowire suspended between the first structure and the second structure leaving a space between the first nanowire and the substrate, the first nanowire having a first film substantially uniformly disposed on a surface thereof, and a first gate structure between the first structure and the second structure, the first gate structure surrounding a portion of the first nanowire leaving uncovered a first portion of the first nanowire between the first gate structure and the first structure and a second portion of the first nanowire between the first gate structure and the second structure, a third structure disposed on the substrate, a fourth structure disposed on the substrate, a second nanowire suspended between the third structure and the fourth structure leaving a space between the second nanowire and the substrate, the second nanowire having a second film substantially uniformly disposed on a surface thereof, and a second gate structure between the third structure and the fourth structure, the second gate structure surrounding a portion of the second nanowire leaving uncovered a first portion of the second nanowire between the second gate structure and the third structure and a second portion of the second nanowire between the second gate structure and the fourth structure, where the first film defines a first layer and the second film defines a second layer, the first layer and the second layer each comprising nickel and at least one of silicide and carbide, where the first film is doped with a first dopant, where the second film is doped with a second dopant that is different from the first dopant, and where the semiconductor device is formed in accordance with a process comprising:
masking the second nanowire, the third structure, the fourth structure, and the second gate structure, and performing atomic layer deposition to deposit the first film at least on a surface of the first nanowire;
masking the first nanowire, the first structure, the second structure, and the first gate structure, and performing a second atomic layer deposition to deposit the second film at least on a surface of the second nanowire;
performing a heat treatment on the semiconductor device to form the first layer, from the first film, on at least a portion of the first nanowire, and to form the second layer, from the second film, on the second nanowire, where the first layer and the second layer substantially evenly coat the at least a portion of the first nanowire and at least a portion of the second nanowire; and
removing any unreacted portions of the first film and the second film.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, where one of the first nanowire and the second nanowire comprises a silicon nanowire or a carbon nanotube.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, where at least the first structure, the second structure, the first nanowire, and the first gate structure comprise parts of a gate-all-around field effect transistor.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, where at least the first structure, the second structure, the first nanowire, and the first gate structure comprise parts of a field effect transistor, where the first structure comprises a source and the second structure comprises a drain.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, where at least the first structure, the second structure, the first nanowire, and the first gate structure comprise parts of a field effect transistor, where the first structure comprises a Schottky junction source and the second structure comprises a Schottky junction drain.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, where at least the first film comprises a metal.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, where at least the first nanowire is not in direct contact with the substrate and the substrate does not comprise the first structure or the second structure.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, where the first nanowire comprises a wire-shaped structure having a thickness constrained to tens of nanometers or less.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, where the substrate comprises a buried oxide layer overlying a semiconductor layer.

### Claim 10

A semiconductor device comprising:
a substrate;
a first structure;
a second structure;
a nanowire suspended between the first structure and the second structure leaving a space between the nanowire and the substrate; and
a gate structure between the first structure and the second structure leaving a first space between the first structure and the gate structure and a second space between the second structure and the gate structure, the gate structure surrounding at least a portion of the nanowire,
where the first structure and the second structure overly the substrate, and the nanowire comprises a layer on a surface of the nanowire,
where the layer comprises nickel and at least one of silicide and carbide, where the layer has a substantially uniform shape, and where the substantially uniform shape comprises a substantially uniform coverage of the surface of the nanowire to reduce stress in the nanowire.