# US 9,437,675 B1 · eDRAM for planar III-V semiconductor devices

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,437,675 B1
- Document ID: US9437675B1
- Status: Granted
- Kind: B1
- Application number: 14/738,073
- Filed: 2015-06-12
- Granted: 2016-09-06
- Earliest claimed: 2015-06-12
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Bruce B. Doris; Ali Khakifirooz; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US9437675B1

## CPC

- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10B 12/038: {the capacitor being in a trench in the substrate}
- H10B 12/37: {the capacitor being at least partially in a trench in the substrate}
- H10B 12/50: {Peripheral circuit region structures}
- H10D 1/665: {Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors}
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 62/854: further characterised by the dopants
- H10D 84/0123: {Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs}
- H10D 84/05: using Group III-V technology
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/3214: {being Group IIIA-VA semiconductors}
- H10P 14/3421: {Arsenides}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Electronic devices including eDRAM structures are formed with a semi-insulating III-V semiconductor layer that suppresses parasitic leakage between the eDRAM transistor and the buried plate of an operatively associated trench capacitor. A low bandgap III-V semiconductor layer is used to form the buried plate.

## Claims

### Claim 1

A method comprising:
obtaining a structure including:
a substrate,
a first III-V semiconductor layer on the substrate, the first III-V semiconductor layer including a low bandgap layer, and
a semi-insulating III-V semiconductor layer on the first III-V semiconductor layer;
forming a plurality of first field effect transistors on a first region of the semi-insulating III-V semiconductor layer, each of the first field effect transistors including a channel region containing III-V material;
forming a plurality of second field effect transistors on a second region of the semi-insulating III-V semiconductor layer, and
forming a plurality of trench capacitors extending through the second region of the semi-insulating III-V semiconductor layer and within the low bandgap layer of the first III-V semiconductor layer such that each of the trench capacitors is in electrical communication with at least one of the second field effect transistors.

### Claim 2 (depends on 1)

The method of claim 1, wherein the step of forming the plurality of trench capacitors further includes doping the first III-V semiconductor layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the step of obtaining the structure includes:
obtaining the substrate;
forming the first III-V semiconductor layer as a blanket layer on the substrate;
introducing dopants within the low bandgap layer of the first III-V semiconductor layer during formation thereof, and
forming the semi-insulating III-V semiconductor layer on the first III-V semiconductor layer.

### Claim 4 (depends on 3)

The method of claim 3, further including the step of forming a trench through the semi-insulating III-V semiconductor layer and filling the trench with electrically conductive contact material in electrical communication with the first III-V semiconductor layer.

### Claim 5 (depends on 3)

The method of claim 3, wherein the step of forming the plurality of trench capacitors further includes forming a plurality of trenches extending through the semi-insulating III-V semiconductor layer and into the first III-V semiconductor layer such that the low bandgap layer of the first III-V semiconductor layer adjoins the trenches, forming a dielectric layer within the trenches, and forming a capacitor electrode on the dielectric layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the capacitor electrodes and the second field effect transistors are formed such that each of the capacitor electrodes is in electrical communication with at least one of the second field effect transistors.

### Claim 7 (depends on 6)

The method of claim 6, wherein the low bandgap layer of the first III-V semiconductor layer consists essentially of n-doped InGaAs or n-doped InAs.

### Claim 8 (depends on 7)

The method of claim 7, wherein the first III-V semiconductor layer further includes a III-V buffer layer between the substrate and the low bandgap layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein the substrate consists essentially of monocrystalline silicon.

### Claim 10 (depends on 8)

The method of claim 8 wherein the buffer layer on the silicon substrate includes GaAs and InP layers.

### Claim 11 (depends on 10)

The method of claim 10, wherein the buffer layer is between 300 nm and 5000 nm thick.

### Claim 12

An eDRAM structure comprising:
a substrate;
a first III-V semiconductor layer on the substrate, the first III-V semiconductor layer including a low bandgap layer;
a semi-insulating III-V semiconductor layer on the first III-V semiconductor layer;
a plurality of first field effect transistors on a first region of the semi-insulating III-V semiconductor layer, each of the first field effect transistors including a channel region containing III-V material;
a plurality of second field effect transistors on a second region of the semi-insulating III-V semiconductor layer, and
a plurality of trench capacitors extending through the second region of the semi-insulating III-V semiconductor layer and within the low bandgap layer of the first III-V semiconductor layer, each of the trench capacitors including a buried plate comprised of the low bandgap layer of the first III-V semiconductor layer, a capacitor electrode, and a dielectric layer between the buried plate and capacitor electrode, each of the capacitor electrodes being in electrical communication with at least one of the second field effect transistors, the semi-insulating III-V semiconductor layer being operable to suppress parasitic leakage between each of the second field effect transistors and each of the buried plate.

### Claim 13 (depends on 12)

The eDRAM structure of claim 12, wherein the low bandgap layer of the first III-V semiconductor layer comprises one or more n-doped regions.

### Claim 14 (depends on 13)

The eDRAM structure of claim 13, wherein the low bandgap layer of the first III-V semiconductor layer consists essentially of n-doped InGaAs or n-doped InAs.

### Claim 15 (depends on 14)

The eDRAM structure of claim 14, wherein the substrate consists essentially of monocrystalline silicon, and wherein the first III-V semiconductor layer further includes a buffer layer between the substrate and the low bandgap layer.

### Claim 16 (depends on 15)

The eDRAM structure of claim 15, further including an electrically conductive contact extending through the semi-insulating III-V semiconductor layer and electrically communicating with the buried plate.

### Claim 17 (depends on 16)

The eDRAM structure of claim 16, wherein the semi-insulating III-V semiconductor layer has a thickness between 100 nm to 1000 nm.

### Claim 18

An eDRAM structure comprising:
a substrate;
a first III-V semiconductor layer on the substrate, the first III-V semiconductor layer including a low bandgap layer;
a semi-insulating III-V semiconductor layer on the first III-V semiconductor layer;
an eDRAM structure including a trench capacitor extending through the semi-insulating III-V semiconductor layer and within the low bandgap layer of the first III-V semiconductor layer and a field effect transistor on the semi-insulating III-V semiconductor layer, the trench capacitor including a buried plate comprised of the low bandgap layer of the first III-V semiconductor layer, a capacitor electrode, and a dielectric layer between the buried plate and capacitor electrode, the capacitor electrode being in electrical communication with the field effect transistor, the semi-insulating III-V semiconductor layer being operable to suppress parasitic leakage between the field effect transistor and the buried plate, and
an electrically conductive contact extending through the semi-insulating III-V semiconductor layer and electrically communicating with the buried plate.

### Claim 19 (depends on 18)

The eDRAM structure of claim 18, wherein the field effect transistor includes a channel region consisting essentially of III-V material.

### Claim 20 (depends on 19)

The structure of claim 19, wherein the substrate consists essentially of monocrystalline silicon.