# US 9,437,673 B2 · Floating guard ring for HV interconnect > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,673 B2 - Document ID: US9437673B2 - Status: Granted - Kind: B2 - Application number: 14/173,692 - Filed: 2014-02-05 - Published: 2015-08-06 - Granted: 2016-09-06 - Earliest claimed: 2014-02-05 - Assignees: Alpha and Omega Semiconductor Incorporated - Applicants: Alpha and Omega Semiconductor Incorporated - Inventors: Shekar Mallikarjunaswamy - Web page: https://patentgrep.com/patent/US9437673B2 ## CPC - H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions} - H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]} - H10D 84/401: {Combinations of FETs or IGBTs with BJTs} - H10D 84/83: of only insulated-gate FETs [IGFET] - H10D 62/109: {Reduced surface field [RESURF] PN junction structures} - H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates} - H10D 84/0188: {Manufacturing their isolation regions} - H10D 84/0191: {Manufacturing their doped wells} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/85: Complementary IGFETs, e.g. CMOS - H10W 10/031: {of isolation regions comprising PN junctions} - H10W 10/30: Isolation regions comprising PN junctions - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Aspects of the present disclosure describe an integrated circuit comprises a substrate of a first conductivity type semiconductor, a lightly doped semiconductor layer of the first conductivity type semiconductor disposed over the substrate, a driver circuit, an electrically conductive interconnect structure formed over the semiconductor layer and electrically connected to the driver circuit at one end, at least one guard structure formed in the semiconductor layer and under the interconnect structure and a well region of the first conductivity type semiconductor formed in a top portion of the semiconductor layer, between the driver circuit and the at least one guard structure and under the interconnect structure. The guard structure is electrically floating. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. ## Claims ### Claim 1 An integrated circuit, comprising: a substrate of a first conductivity type semiconductor; a lightly doped semiconductor layer of the first conductivity type semiconductor disposed over the substrate; a driver circuit including a first doped region of a second conductivity type semiconductor disposed in the semiconductor layer; an electrically conductive interconnect structure formed over the semiconductor layer and electrically connected to the driver circuit at one end; at least one guard structure formed in the semiconductor layer and under the interconnect structure, wherein the at least one guard structure is electrically floating; and a well region of the first conductivity type semiconductor formed in a top portion of the semiconductor layer and under the interconnect structure, wherein the well region is disposed between the driver circuit and the at least one guard structure and wherein the well region is doped heavier than the semiconductor layer. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the at least one guard structure includes a region of the second conductivity type semiconductor formed in the semiconductor layer of the first conductivity type semiconductor. ### Claim 3 (depends on 1) The integrated circuit of claim 1, wherein the at least one guard structure includes a trench filled with a conductor material, that is electrically isolated from the semiconductor layer of the first conductivity type semiconductor. ### Claim 4 (depends on 1) The integrated circuit of claim 1, wherein the at least one guard structure includes a trench filled with an insulating material. ### Claim 5 (depends on 1) The integrated circuit of claim 1 further comprising an insulating layer formed between the interconnect structure and the semiconductor layer of the first conductivity type semiconductor. ### Claim 6 (depends on 1) The integrated circuit of claim 1, wherein the driver circuit further includes a second well region of the second conductivity type semiconductor in the first doped region and a second doped region of the second conductivity type semiconductor in the second well region. ### Claim 7 (depends on 1) The integrated circuit of claim 1, wherein the first conductivity type semiconductor is a P-type semiconductor and the second conductivity type semiconductor is an N-type semiconductor. ### Claim 8 (depends on 1) The integrated circuit of claim 1, wherein the first conductivity type semiconductor is an N-type semiconductor and the second conductivity type semiconductor is a P-type semiconductor. ### Claim 9 (depends on 1) The integrated circuit of claim 1, wherein the interconnect structure is at high voltage in a range from about 120 volts to about 1200 volts. ### Claim 10 (depends on 1) The integrated circuit of claim 1, wherein the interconnect structure has a second end that is electrically connected to a drain region of a level shifter. ### Claim 11 (depends on 1) The integrated circuit of claim 1, wherein the at least one guard structure has a doping concentration that is in a range from about 5×1015 atoms/centimeter3 to about 1×1016 atoms/centimeter3. ### Claim 12 An integrated circuit, comprising: a substrate of a first conductivity type semiconductor; a lightly doped semiconductor layer of the first conductivity type semiconductor disposed over the substrate; a driver circuit including a first doped region of a second conductivity type semiconductor disposed in the semiconductor layer; a level shifter including a second doped region of the second conductivity type semiconductor disposed in the semiconductor layer and a drain region in the second doped region, wherein the drain region of the level shifter is electrically connected to the driver circuit by an electrically conductive interconnect structure; a termination structure, wherein the termination structure surrounds both the driver circuit and the level shifter, whereby the driver circuit and level shifter are located within the same termination structure; and at least one guard structure formed in the semiconductor layer between the driver circuit and the level shifter and under the interconnect structure, wherein the at least one well region is electrically floating. ### Claim 13 (depends on 12) The integrated circuit of claim 12, wherein the at least one guard structure includes a region of the first conductivity type semiconductor formed in the semiconductor layer of the first conductivity type semiconductor. ### Claim 14 (depends on 12) The integrated circuit of claim 12, wherein the at least guard structure includes a trench filled with a conductor material, that is electrically isolated from the semiconductor layer of the first conductivity type semiconductor. ### Claim 15 (depends on 12) The integrated circuit of claim 12, wherein the at least one guard structure includes a trench filled with an insulating material. ### Claim 16 (depends on 12) The integrated circuit of claim 12 further comprising an insulating layer formed between the interconnect structure and the semiconductor layer of the first conductivity type semiconductor. ### Claim 17 (depends on 12) The integrated circuit of claim 12, wherein the driver circuit further includes a well region of the second conductivity type semiconductor in the first doped region and a third doped region of the second conductivity type semiconductor in the second well region. ### Claim 18 (depends on 12) The integrated circuit of claim 12, wherein the interconnect structure is at high voltage in a range from about 120 volts to about 1200 volts. ### Claim 19 (depends on 12) The integrated circuit of claim 12, wherein the at least one guard structure has a doping concentration that is in a range from about 1×1016 atoms/centimeter3 to about 5×1016 atoms/centimeter3. ### Claim 20 (depends on 12) The integrated circuit of claim 12, wherein the driver circuit and the drain region of the level shifter are disposed in a high voltage circuit region and separated from a low voltage circuit region by an insulating structure.