# US 9,437,672 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,672 B2 - Document ID: US9437672B2 - Status: Granted - Kind: B2 - Application number: 14/056,351 - Filed: 2013-10-17 - Published: 2014-07-31 - Granted: 2016-09-06 - Earliest claimed: 2013-01-29 - Assignees: Fujitsu Limited - Applicants: Fujitsu Limited - Inventors: Naoya Okamoto - Web page: https://patentgrep.com/patent/US9437672B2 ## CPC - H10D 62/405: {Orientations of crystalline planes} - H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT} - H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs} - H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts} - H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)} - H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device includes: a first semiconductor layer of a nitride semiconductor formed on a substrate; a second semiconductor layer of a nitride semiconductor formed on the first semiconductor layer; and a gate electrode, a source electrode, a drain electrode, and a hole extraction electrode, each of which is formed on the second semiconductor layer, wherein between the source electrode and the hole extraction electrode or in a region right under the source electrode, the first semiconductor layer and the second semiconductor layer form a vertical interface approximately perpendicular to a surface of the substrate, and a surface of the first semiconductor layer configured to form the vertical interface is an N-polar surface. ## Claims ### Claim 1 A semiconductor device comprising: a first semiconductor layer of a nitride semiconductor formed on a substrate; a first recess portion formed on a surface of the first semiconductor layer in a first region of the semiconductor device; a second semiconductor layer of a nitride semiconductor formed on a bottom and a side surface of the first recess portion and on the surface of the first semiconductor layer in a second region of the semiconductor device; and a second recess portion formed on a surface of the second semiconductor layer in the first region of the semiconductor device; a hole extraction electrode formed in the second recess portion and on the second semiconductor layer in the first region of the semiconductor device; a gate electrode, a source electrode and a drain electrode formed on the second semiconductor layer in the second region of the semiconductor device, wherein the side surface of the first recess portion configured to form a vertical interface, the vertical interface of the first semiconductor layer includes N atoms at the surface referred to as an N-polar surface. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the vertical interface of the first semiconductor layer is formed by removing a part of the first semiconductor layer, the gate electrode, the source electrode, and the drain electrode are formed in a region in which the first semiconductor layer is not removed, and the hole extraction electrode is formed in a region in which the part of the first semiconductor layer is removed. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the surface of the first semiconductor layer parallel to the surface of the substrate is a non-polar surface. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein a surface of the substrate is an a-plane or an m-plane of crystal plane orientation. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein a surface of the substrate is perpendicular to a c-plane of crystal plane orientation and is located between an m-plane and an a-plane of crystal plane orientation. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the substrate is one of an m-plane AlN substrate, an m-plane SiC substrate, a γ-LiAlO2 (100) substrate, an m-plane ZnO substrate, an m-plane sapphire substrate, an a-plane sapphire substrate having a patterned surface, a Si (112) substrate having a patterned surface, an a-plane GaN substrate, an a-plane AlN substrate, an a-plane ZnO substrate, an a-plane SiC substrate, an r-plane sapphire substrate, and a LiGaO2 (010) substrate. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the substrate is a substrate having a surface on which a film of m-plane AlN, m-plane SiC, γ-LiAlO2 (100), m-plane ZnO, m-plane sapphire, a-plane sapphire having a patterned surface, Si (112) having a patterned surface, a-plane GaN, a-plane AlN, a-plane ZnO, a-plane SiC, r-plane sapphire, or LiGaO2 (010) is formed. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the second semiconductor layer is a first conductive type semiconductor layer. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein the first conductive type indicates an n-type conductivity. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, further comprising a second conductive type semiconductor layer between the second semiconductor layer and the gate electrode. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, further comprising a second conductive type semiconductor layer between the second semiconductor layer and the hole extraction electrode. ### Claim 12 (depends on 10) The semiconductor device according to claim 10, wherein the second conductive type indicates a p-type conductivity. ### Claim 13 (depends on 1) The semiconductor device according to claim 1, wherein the vertical interface is a first vertical interface, the first semiconductor layer and the second semiconductor layer form a second vertical interface right under the drain electrode so as to be approximately perpendicular to the surface of the substrate, and a surface of the first semiconductor layer configured to form the second vertical interface is a Ga-polar surface. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, wherein the vertical interface is a first vertical interface, the first semiconductor layer and the second semiconductor layer form a second vertical interface right under the drain electrode so as to be approximately perpendicular to the surface of the substrate, and a surface of the first semiconductor layer configured to form the second vertical interface is along the (0001) plane. ### Claim 15 (depends on 1) The semiconductor device according to claim 1, wherein the hole extraction electrode is grounded. ### Claim 16 (depends on 1) The semiconductor device according to to claim 1, further comprising a backside-surface electrode on a backside surface of the substrate, wherein the hole extraction electrode and the backside-surface electrode are electrically connected to each other with a through electrode configured to penetrate through the substrate. ### Claim 17 (depends on 1) The semiconductor device according to claim 1, wherein the first semiconductor layer includes a material containing GaN. ### Claim 18 A semiconductor device comprising: a first semiconductor layer of a nitride semiconductor formed on a substrate; a first recess portion formed on a surface of the first semiconductor layer in a first region of the semiconductor device; a second semiconductor layer of a nitride semiconductor formed on a bottom and a side surface of the first recess portion and on the surface of the first semiconductor layer in a second region of the semiconductor device; and a second recess portion formed on a surface of the second semiconductor layer in the first region of the semiconductor device; a hole extraction electrode formed in the second recess portion and on the second semiconductor layer in the first region of the semiconductor device; a gate electrode, a source electrode and a drain electrode formed on the second semiconductor layer in the second region of the semiconductor device, wherein the vertical interface of the first semiconductor layer having a (000-1) plane of crystal plane orientation.