# US 9,437,661 B2 · Thin film transistor substrate, display device having the same and method of manufacturing the same

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- Number: US 9,437,661 B2
- Document ID: US9437661B2
- Status: Granted
- Kind: B2
- Application number: 14/877,044
- Filed: 2015-10-07
- Published: 2016-01-28
- Granted: 2016-09-06
- Earliest claimed: 2013-07-31
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Do-Hyun Kwon; Min-Jung Lee; Sung-Eun Lee; Il-Jeong Lee; Jung-Kyu Lee; Kwang-Young Choi
- Web page: https://patentgrep.com/patent/US9437661B2

## CPC

- H10K 59/1213: {the pixel elements being TFTs}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10K 59/1201: {Manufacture or treatment}
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A thin film transistor substrate includes a semiconductor pattern on a base substrate, a first insulation member disposed on the semiconductor pattern, a second insulation pattern disposed on the first insulation member, and a gate electrode disposed on the first insulation member and the second insulation pattern. The second insulation pattern overlaps a first end portion of the semiconductor pattern, and exposes a second end portion of the semiconductor pattern opposite to the first end portion. The gate electrode overlaps both the first insulation member and the second insulation pattern.

## Claims

### Claim 1

A method of manufacturing a thin film transistor substrate, comprising:
sequentially forming a semiconductor layer, a first insulation layer and a second insulation layer, on a base substrate;
forming a first photoresist pattern on the second insulation layer and having a first thickness portion, and a second thickness portion thinner than the first thickness portion;
removing exposed portions of the second insulation layer, the first insulation layer and the semiconductor layer using the first photoresist pattern as a mask, to form an intermediate insulation pattern, a first insulation pattern and a semiconductor pattern from the second insulation layer, the first insulation layer and the semiconductor layer, respectively;
reducing an entirety of the first photoresist pattern by a thickness of the second thickness portion, to form a second photoresist pattern having a third thickness and expose a portion of the intermediate insulation pattern;
removing the exposed portion of the intermediate insulation pattern using the second photoresist pattern as a mask, to form a second insulation pattern from the intermediate insulation pattern; and
forming a gate electrode on and overlapping both the first insulation pattern and the second insulation pattern.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first insulation pattern comprises a material having a dielectric constant greater than about 10.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
forming an inorganic insulation layer on the base substrate comprising the gate electrode thereon;
forming a first contact hole penetrating the inorganic insulation layer, the second insulation pattern and the first insulation pattern, to partially expose a first end portion of the semiconductor pattern, and forming a second contact hole penetrating the inorganic insulation layer and the first insulation pattern, to partially expose a second end portion of the semiconductor pattern; and
forming a drain electrode electrically connected to the first end portion of the semiconductor pattern through the first contact hole, and forming a source electrode electrically connected to the second end portion of the semiconductor pattern through the second contact hole.