# US 9,437,657 B2 · Solid state devices having fine pitch structures > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,657 B2 - Document ID: US9437657B2 - Status: Granted - Kind: B2 - Application number: 14/616,128 - Filed: 2015-02-06 - Published: 2015-06-04 - Granted: 2016-09-06 - Earliest claimed: 2012-11-13 - Assignees: HGST, Inc. - Applicants: HGST, Inc. - Inventors: Daniel R. Shepard - Web page: https://patentgrep.com/patent/US9437657B2 ## CPC - H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays} - H10B 63/20: {comprising selection components having two electrodes, e.g. diodes} - H10N 70/066: {by filling of openings, e.g. damascene method} - H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect} - H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices} - H10N 70/8828: {Tellurides, e.g. GeSbTe} - H10P 50/28: of insulating materials - H10P 50/73: {using masks for insulating materials} - H10P 76/4085: {characterised by the processes involved to create the masks} - H10B: ELECTRONIC MEMORY DEVICES - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract In various embodiments, a method for forming a memory array includes forming a plurality of rows and columns of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes. The corners of the holes can be rounded. ## Claims ### Claim 1 A method for forming an array, the method comprising: forming a plurality of rows of hardmask material above one or more layers of insulating material; forming a plurality of columns of hardmask material above the plurality of rows of hardmask material; etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material; and forming memory cells in the holes, wherein a first subset of the plurality of rows are formed by a lithographic step and wherein a second subset of the plurality of rows are thereafter formed by a deposition step, wherein the second subset of the plurality of rows are deposited between the first subset of the plurality of rows; and wherein the first subset of the plurality of rows are separated by a distance corresponding to at least double a distance between array bitlines. ### Claim 2 (depends on 1) The method of claim 1, wherein forming the plurality of rows of hardmask material comprises forming a plurality of rows of insulating material and depositing a layer of hardmask material on top of the plurality of rows of insulating material. ### Claim 3 (depends on 1) The method of claim 1, wherein a first subset of the plurality of columns are formed by a lithographic step and wherein a second subset of the plurality of columns are thereafter formed by a deposition step. ### Claim 4 (depends on 3) The method of claim 3, wherein the deposition step comprises forming sidewall hardmask features on the sides the first subset of the plurality of columns and depositing the second subset of the plurality of columns, wherein a thickness of sidewall material in the sidewall hardmask features is defined by the deposition step. ### Claim 5 (depends on 1) The method of claim 1, wherein etching the holes comprises performing a selective etch of the insulating material, wherein the insulating material comprises at least two different types of insulating materials, and wherein the selectively etched hole comprises a first diameter etched in a first type of insulating material and a second diameter larger than the first diameter etched in a second type of insulating material. ### Claim 6 (depends on 1) The method of claim 1, further comprising forming an electronic circuit in electrical communication with the array. ### Claim 7 An electronic circuit in the form of an array comprising features that have been formed by forming a plurality of rows of hardmask material above one or more layers of insulating material, forming a plurality of columns of hardmask material above the plurality of rows of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes, wherein a first subset of the plurality of rows are formed by a lithographic step and wherein a second subset of the plurality of rows are thereafter formed by a deposition step, and wherein the second subset of the plurality of rows are deposited between the first subset of the plurality of rows: wherein the first subset of the plurality of rows are separated by a distance corresponding to double a distance between array bitlines. ### Claim 8 (depends on 7) The electronic circuit of claim 7, wherein forming the plurality of rows of hardmask material comprises forming a plurality of rows of insulating material and depositing a layer of hardmask material on top of the plurality of rows of insulating material. ### Claim 9 (depends on 7) The electronic circuit of claim 7, wherein a first subset of the plurality of rows are formed by a lithographic step and wherein a second subset of the plurality of rows are thereafter formed by a deposition step. ### Claim 10 (depends on 9) The electronic circuit of claim 9, wherein the deposition step comprises forming sidewall hardmask features on the sides the first subset of the plurality of rows and depositing the second subset of the plurality of rows, wherein a thickness of sidewall material in the sidewall hardmask features is defined by the deposition step. ### Claim 11 (depends on 7) The electronic circuit of claim 7, wherein a first subset of the plurality of columns are formed by a lithographic step and wherein a second subset of the plurality of columns are thereafter formed by a deposition step. ### Claim 12 (depends on 11) The electronic circuit of claim 11, wherein the deposition step comprises forming sidewall hardmask features on the sides the first subset of the plurality of columns and depositing the second subset of the plurality of columns, wherein a thickness of sidewall material in the sidewall hardmask features is defined by the deposition step. ### Claim 13 An electronic system comprising one or more array circuits, the array circuits comprising features that have been formed by forming a plurality of rows of hardmask material above one or more layers of insulating material, forming a plurality of columns of hardmask material above the plurality of rows of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes, wherein a first subset of the plurality of rows are formed by a lithographic step and wherein a second subset of the plurality of rows are thereafter formed by a deposition step, and wherein the second subset of the plurality of rows are deposited between the first subset of the plurality of rows; wherein the first subset of the plurality of rows are separated by a distance corresponding to double a distance between array bitlines. ### Claim 14 (depends on 13) The electronic system of claim 13, wherein forming the plurality of rows of hardmask material comprises forming a plurality of rows of insulating material and depositing a layer of hardmask material on top of the plurality of rows of insulating material. ### Claim 15 (depends on 13) The electronic system of claim 13, wherein a first subset of the plurality of rows are formed by a lithographic step and wherein a second subset of the plurality of rows are thereafter formed by a deposition step. ### Claim 16 (depends on 15) The electronic system of claim 15, wherein a first subset of the plurality of rows are formed by a lithographic step and wherein a second subset of the plurality of rows are thereafter formed by a deposition step. ### Claim 17 (depends on 16) The electronic system of claim 16, wherein the deposition step comprises forming sidewall hardmask features on the sides the first subset of the plurality of rows and depositing the second subset of the plurality of rows, wherein a thickness of sidewall material in the sidewall hardmask features is defined by the deposition step. ### Claim 18 (depends on 15) The electronic system of claim 15, wherein a first subset of the plurality of columns are formed by a lithographic step and wherein a second subset of the plurality of columns are thereafter formed by a deposition step. ### Claim 19 (depends on 18) The electronic system of claim 18, wherein the deposition step comprises forming sidewall hardmask features on the sides the first subset of the plurality of columns and depositing the second subset of the plurality of columns, wherein a thickness of sidewall material in the sidewall hardmask features is defined by the deposition step. ### Claim 20 (depends on 13) The electronic circuit of claim 13, wherein the holes in which memory cells are formed have corners and these corners are rounded.