# US 9,437,656 B2 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,656 B2 - Document ID: US9437656B2 - Status: Granted - Kind: B2 - Application number: 14/515,205 - Filed: 2014-10-15 - Published: 2015-02-26 - Granted: 2016-09-06 - Earliest claimed: 2010-03-24 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Kabushiki Kaisha Toshiba - Inventors: Yoshiaki Fukuzumi; Hideaki Aochi - Web page: https://patentgrep.com/patent/US9437656B2 ## CPC - H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays} - G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites} - G11C 16/04: using variable threshold transistors, e.g. FAMOS - H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors} - H10W 20/43: Layouts of interconnections - H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses - G11C 2213/73: Array where access device function, e.g. diode function, being merged with memorizing function of memory element - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor memory device according to one embodiment of the present invention includes a dielectric film configured to store information depending on presence or absence of a conductive path therein, and a plurality of electrodes provided to contact a first surface of the dielectric film. The conductive path can be formed between two electrodes arbitrarily selected form the plurality of electrodes. The conductive path has a rectifying property of allowing a current to flow more easily in a first direction connecting arbitrary two electrodes than in a second direction opposite to the first direction. The largest possible number of the conductive paths that may be formed is larger than the number of the plurality of electrodes. ## Claims ### Claim 1 A semiconductor memory device, comprising: a first, a second, a third and a fourth bit line extending in a first direction; a first, a second, a third and a fourth electrode arranged in a second direction intersecting the first direction; a fifth electrode extending in the second direction; a first dielectric film having a first surface and a second surface being opposite to the first surface, the first, second, third and fourth electrodes provided to contact the first surface, and the fifth electrode provided to contact the second surface; a first transistor coupled to the first electrode and coupled to the first bit line; a second transistor coupled to the second electrode and coupled to the second bit line; a third transistor coupled to the third electrode and coupled to the third bit line; a fourth transistor coupled to the fourth electrode and coupled to the fourth bit line; a first word line extending in the second direction and serving as a first gate electrode of the first transistor, as a second gate electrode of the second transistor, as a third gate electrode of the third transistor, and as a fourth gate electrode of the fourth transistor; a control circuit configured to execute a write operation of forming a conductive path in the first dielectric film; a sixth, a seventh, an eighth and a ninth electrode arranged in the second direction; a tenth electrode extending in the second direction; a second dielectric film having a third surface and a fourth surface being opposite to the third surface, the sixth, seventh, eighth and ninth electrodes provided to contact the third surface, and the tenth electrode provided to contact the fourth surface; a fifth transistor coupled to the sixth electrode and coupled to the first bit line; a sixth transistor coupled to the seventh electrode and coupled to the second bit line; a seventh transistor coupled to the eighth electrode and coupled to the third bit line; an eighth transistor coupled to the ninth electrode and coupled to the fourth bit line; and a second word line extending in the second direction and serving as a fifth gate electrode of the fifth transistor, as a sixth gate electrode of the sixth transistor, as a seventh gate electrode of the seventh transistor, and as an eighth gate electrode of the eighth transistor. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein the fifth and tenth electrodes are controlled independently. ### Claim 3 (depends on 1) The semiconductor memory device according to claim 1, wherein the fifth and tenth electrodes are controlled simultaneously. ### Claim 4 (depends on 1) The semiconductor memory device according to claim 1, further comprising a control circuit configured to execute write and erase operations by applying certain voltages to the first bit line and the first word line. ### Claim 5 (depends on 1) The semiconductor memory device according to claim 1, wherein the control circuit is configured to execute a read operation of whether the conductive path is present or absent. ### Claim 6 (depends on 1) The semiconductor memory device according to claim 1, wherein the control circuit is configured to execute a write operation of forming a rectifying conductive path in the first dielectric film. ### Claim 7 (depends on 1) The semiconductor memory device according to claim 1, wherein the control circuit is configured to execute a write operation of forming a conductive path in the first dielectric film by applying certain voltages to the first electrode, while the second electrode is floating. ### Claim 8 (depends on 1) The semiconductor memory device according to claim 1, wherein the control circuit executes an erase operation of returning the first dielectric film to its initial state by applying a first voltage to the fifth electrode and by applying a second voltage being bigger than the first voltage to the one of the first electrode through the first transistor and the first bit line. ### Claim 9 (depends on 1) The semiconductor memory device according to claim 1, wherein the fifth electrode is positioned higher than the first word line. ### Claim 10 (depends on 1) The semiconductor memory device according to claim 1, wherein the first bit line is positioned higher than the first word line. ### Claim 11 (depends on 1) The semiconductor memory device according to claim 1, wherein the fifth electrode is positioned higher than the first word line, and the first bit line is positioned higher than the first word line. ### Claim 12 (depends on 1) The semiconductor memory device according to claim 1, further comprising a first contact connected between the first bit line and a semiconductor substrate, and a second contact connected between the first electrode and the semiconductor substrate, wherein the first transistor is formed on the semiconductor substrate. ### Claim 13 (depends on 1) The semiconductor memory device according to claim 1, further including a column decoder configured to drive the first bit line, and a row decoder configured to drive the first word line. ### Claim 14 (depends on 1) The semiconductor memory device according to claim 1, wherein the conductive path is a filament. ### Claim 15 A semiconductor memory device, comprising: a first, a second, a third and a fourth bit line extending in a first direction; a first, a second, a third and a fourth electrode arranged in a second direction intersecting the first direction; a fifth electrode extending in the second direction; a first dielectric film having a first surface and a second surface being opposite to the first surface, the first, second, third and fourth electrodes provided to contact the first surface, and the fifth electrode provided to contact the second surface; a first transistor coupled to the first electrode and coupled to the first bit line; a second transistor coupled to the second electrode and coupled to the second bit line; a third transistor coupled to the third electrode and coupled to the third bit line; a fourth transistor coupled to the fourth electrode and coupled to the fourth bit line; a first word line extending in the second direction and serving as a first gate electrode of the first transistor, as a second gate electrode of the second transistor, as a third gate electrode of the third transistor, and as a fourth gate electrode of the fourth transistor; and a control circuit configured to execute a write operation of forming a conductive path in the first dielectric film by applying certain voltages to the first electrode, while the second electrode is floating. ### Claim 16 (depends on 15) The semiconductor memory device according to claim 15, wherein the control circuit is configured to execute a read operation of whether the conductive path is present or absent. ### Claim 17 (depends on 15) The semiconductor memory device according to claim 15, wherein the control circuit is configured to execute a write operation of forming a rectifying conductive path in the first dielectric film. ### Claim 18 (depends on 15) The semiconductor memory device according to claim 15, wherein the control circuit executes an erase operation of returning the first dielectric film to its initial state by applying a first voltage to the fifth electrode and by applying a second voltage higher than the first voltage to the one of the first electrode through the first transistor and the first bit line. ### Claim 19 (depends on 15) The semiconductor memory device according to claim 15, wherein the fifth electrode is positioned higher than the first word line. ### Claim 20 (depends on 15) The semiconductor memory device according to claim 15, wherein the first bit line is positioned higher than the first word line. ### Claim 21 (depends on 15) The semiconductor memory device according to claim 15, wherein the fifth electrode is positioned higher than the first word line, and the first bit line is positioned higher than the first word line. ### Claim 22 (depends on 15) The semiconductor memory device according to claim 15, further comprising a first contact connected between the first bit line and a semiconductor substrate, and a second contact connected between the first electrode and the semiconductor substrate, wherein the first transistor is formed on the semiconductor substrate. ### Claim 23 (depends on 15) The semiconductor memory device according to claim 15, further including a column decoder configured to drive the first bit line, and a row decoder configured to drive the first word line. ### Claim 24 (depends on 15) The semiconductor memory device according to claim 15, wherein the conductive path is a filament.