# US 9,437,647 B2 · Solid-state image capturing apparatus, method of manufacturing the same, and camera

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- Number: US 9,437,647 B2
- Document ID: US9437647B2
- Status: Granted
- Kind: B2
- Application number: 14/635,035
- Filed: 2015-03-02
- Published: 2015-09-17
- Granted: 2016-09-06
- Earliest claimed: 2014-03-14
- Assignees: Canon Kabushiki Kaisha
- Applicants: Canon Kabushiki Kaisha
- Inventors: Mahito Shinohara
- Web page: https://patentgrep.com/patent/US9437647B2

## CPC

- H10F 39/196: {Junction field effect transistor [JFET] image sensors; Static induction transistor [SIT] image sensors}
- H10F 39/014: {of CMOS image sensors}
- H10F 39/197: {Bipolar transistor image sensors}
- H10F 39/8037: {the integrated elements comprising a transistor}
- H10F 39/807: {Pixel isolation structures}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

A solid-state image capturing apparatus, comprising a semiconductor substrate including a first region of a first conductivity type, charge accumulation regions of a second conductivity type, transistors each outputting a signal based on charges accumulated in the charge accumulation region, a second region of the first conductivity type formed in a position deeper than the charge accumulation regions and shallower than the first region so as to be electrically conducted to the first region, whose impurity concentration is higher than that of the first region, and a third region of the second conductivity type formed between the second region and the first region, wherein the second region is formed across a region including two or more transistors in a planar view and supplies a current to each of the two or more transistors.

## Claims

### Claim 1

A solid-state image capturing apparatus comprising:
a semiconductor substrate including a first semiconductor region of a first conductivity type;
a plurality of charge accumulation regions of a second conductivity type formed in the semiconductor substrate;
a plurality of transistors formed in a semiconductor substrate, each configured to output a signal based on a charge accumulated in corresponding one of the plurality of charge accumulation regions;
a second semiconductor region of the first conductivity type formed in a position deeper than the plurality of charge accumulation regions of the semiconductor substrate and shallower than the first semiconductor region, electrically conducted to the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region; and
a third semiconductor region of the second conductivity type formed between the second semiconductor region and the first semiconductor region, and receiving a first power supply voltage,
wherein the second semiconductor region is formed across a region including two or more transistors of the plurality of transistors in a planar view with respect to an upper surface of the semiconductor substrate, and is configured to supply a current to the two or more transistors upon receiving a second power supply voltage different from the first power supply voltage.

### Claim 2 (depends on 1)

The apparatus according to claim 1, further comprising a plurality of fourth semiconductor regions of the second conductivity type formed in the semiconductor substrate and receiving a potential corresponding to an amount of charges accumulated in the plurality of charge accumulation regions,
wherein each of the fourth semiconductor regions acts as a control unit configured to control output potentials from the plurality of transistors.

### Claim 3 (depends on 2)

The apparatus according to claim 2, wherein the plurality of transistors include a junction field effect transistor, and
each of the fourth semiconductor regions forms a gate of the junction field effect transistor.

### Claim 4 (depends on 2)

The apparatus according to claim 2, wherein the plurality of transistors include a static induction transistor, and
each of the fourth semiconductor regions forms a gate of the static induction transistor.

### Claim 5 (depends on 2)

The apparatus according to claim 2, wherein the plurality of transistors include a bipolar transistor, and
each of the fourth semiconductor regions forms a base of the bipolar transistor.

### Claim 6 (depends on 2)

The apparatus according to claim 2, further comprising a plurality of second transistors formed in the semiconductor substrate and configured to transfer the charges accumulated in the plurality of charge accumulation regions to the fourth semiconductor regions.

### Claim 7 (depends on 1)

The apparatus according to claim 1, wherein the third semiconductor region has, in the planar view with respect to the upper surface of the semiconductor substrate, a pattern configured to electrically conduct the first semiconductor region and the second semiconductor region to each other.

### Claim 8 (depends on 1)

The apparatus according to claim 1, wherein the third semiconductor region is formed in a lattice-shaped pattern or a strip-shaped pattern in the planar view with respect to the upper surface of the semiconductor substrate.

### Claim 9 (depends on 8)

The apparatus according to claim 8, wherein the third semiconductor region in the lattice-shaped pattern is formed so as not to electrically isolate, by a depletion layer formed in a boundary portion between the first semiconductor region and the third semiconductor region, a portion of the first semiconductor region above the third semiconductor region and a portion of the first semiconductor region below the third semiconductor region from each other.

### Claim 10 (depends on 1)

The apparatus according to claim 1, further comprising a contact plug configured to supply the first power supply voltage to the third semiconductor region.

### Claim 11 (depends on 10)

The apparatus according to claim 10, further comprising a semiconductor region which electrically connects the third semiconductor region and the contact plug.

### Claim 12 (depends on 1)

The apparatus according to claim 1, further comprising a fifth semiconductor region of the first conductivity type formed, so as to contact the first semiconductor region, in a position deeper than the third semiconductor region of the semiconductor substrate, at an impurity concentration of the first conductivity type higher than that of the first semiconductor region,
wherein the fifth semiconductor region is formed across a region including the two or more transistors in the planar view with respect to the upper surface of the semiconductor substrate.

### Claim 13 (depends on 1)

The apparatus according to claim 1, further comprising a second contact plug configured to supply the second power supply voltage to the first semiconductor region and the second semiconductor region.

### Claim 14 (depends on 13)

The apparatus according to claim 13, further comprising a semiconductor region formed at the impurity concentration of the first conductivity type higher than that of the first semiconductor region and configured to electrically connect the second semiconductor region and the second contact plug.

### Claim 15 (depends on 1)

The apparatus according to claim 1, further comprising an electrode arranged on a surface opposite to a surface in which the plurality of charge accumulation regions on the semiconductor substrate and the plurality of transistors are formed, and configured to supply the second power supply voltage to the first semiconductor region and the second semiconductor region.

### Claim 16 (depends on 1)

The apparatus according to claim 1, further comprising an element isolation region formed in a position shallower than the second semiconductor region of the semiconductor substrate.

### Claim 17 (depends on 16)

The apparatus according to claim 16, wherein the element isolation region is a semiconductor region of the first conductivity type formed so as to contact the first semiconductor region.

### Claim 18 (depends on 17)

The apparatus according to claim 17, wherein the element isolation region is in contact with the second semiconductor region.

### Claim 19 (depends on 1)

A camera comprising:
the solid-state image capturing apparatus defined in claim 1; and
a processing unit configured to process a signal output from the solid-state image capturing apparatus.

### Claim 20

A method of manufacturing a solid-state image capturing apparatus, comprising steps of:
preparing a semiconductor substrate including a first semiconductor region of a first conductivity type;
forming, in the first semiconductor region, a plurality of charge accumulation regions of a second conductivity type having a polarity different from that of the first conductivity type;
forming, in the first semiconductor region in the semiconductor substrate, a plurality of transistors configured to output a current corresponding to an amount of charges accumulated in the plurality of charge accumulation regions; and
forming a second semiconductor region of the first conductivity type across a region including two or more transistors of the plurality of transistors in a planar view with respect to an upper surface of the semiconductor substrate so as to contact the first semiconductor region, in a position deeper than the plurality of charge accumulation regions of the semiconductor substrate, at an impurity concentration of the first conductivity type higher than that of the first semiconductor region.

### Claim 21 (depends on 20)

The method according to claim 20, further comprising a step of forming a third semiconductor region of the second conductivity type so as to contact the first semiconductor region in a position deeper than the second semiconductor region of the semiconductor substrate.

### Claim 22 (depends on 21)

The method according to claim 21, wherein the steps of forming the second semiconductor region and the third semiconductor region includes steps of
forming, on the semiconductor substrate, a resist pattern having an opening on the first semiconductor region in the semiconductor substrate,
forming a first region of the second conductivity type in a position shallower than the third semiconductor region in the first semiconductor region while implanting an impurity of the second conductivity type in the first semiconductor region via the resist pattern and forming the third semiconductor region of the second conductivity type under the opening in the first semiconductor region, and
forming the second semiconductor region of the first conductivity type by implanting an impurity of the first conductivity type in a position having the same depth as that of the first region in the first semiconductor region.

### Claim 23 (depends on 22)

The method according to claim 22, wherein the first region is a region formed by an impurity of the second conductivity type that has passed through the resist pattern.

### Claim 24 (depends on 20)

The method according to claim 20, further comprising a step of forming, in the semiconductor substrate, a plurality of fourth semiconductor regions of the second conductivity type configured to act as a control unit which receives a potential corresponding to an amount of charges accumulated in the plurality of charge accumulation regions and control a current amount of each of the plurality of transistors.