# US 9,437,621 B2 · Method of manufacturing components of display panel assembly from same mother substrate > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,621 B2 - Document ID: US9437621B2 - Status: Granted - Kind: B2 - Application number: 14/946,936 - Filed: 2015-11-20 - Published: 2016-07-14 - Granted: 2016-09-06 - Earliest claimed: 2015-01-12 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Sang-myoung Lee; Osung Seo; Seungjun Yu - Web page: https://patentgrep.com/patent/US9437621B2 ## CPC - H10D 86/60: wherein the TFTs are in active matrices - G02F 1/133351: {Manufacturing of individual cells out of a plurality of cells, e.g. by dicing} - G02F 1/133514: {Colour filters} - G02F 1/13452: {Conductors connecting driver circuitry and terminals of panels} - H10D 86/021: {of multiple TFTs} - H10D 86/411: {characterised by materials, geometry or structure of the substrates} - H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer} - H10D 86/441: {Interconnections, e.g. scanning lines} - G02F 1/133302: {Rigid substrates, e.g. inorganic substrates} - H10D 30/6746: {Amorphous silicon} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS ## Abstract A method of manufacturing a display panel assembly includes: preparing a mother substrate on which are defined first regions and dummy regions respectively between adjacent first regions; forming pixel driving lines and pixels connected to the pixel driving lines on each of the first regions in a same process at the same time as forming circuit connection lines on each of the dummy regions; connecting a driving element which drives the pixels to the circuit connection lines of the dummy regions; dividing the mother substrate to separate the first regions and the dummy regions from each other, each of the separated first regions defining a thin film transistor board of the display panel assembly, and each of the separated dummy regions defining a driving circuit board of the display panel assembly; and connecting the driving circuit board to the thin film transistor board. ## Claims ### Claim 1 A method of manufacturing a display panel assembly, the method comprising: preparing a mother substrate on which are defined a plurality of first regions and a plurality of dummy regions which is respectively between adjacent first regions; forming a plurality of pixel driving lines and a plurality of pixels which is connected to the pixel driving lines on each of the first regions of the mother substrate in a same process at the same time as forming a plurality of circuit connection lines on each of the dummy regions of the mother substrate; connecting a driving element which drives the plurality of pixels to the circuit connection lines of the dummy regions of the mother substrate; dividing the mother substrate including the pixel driving lines, the pixels and the circuit connection lines formed thereon to separate the first regions with the pixel driving lines and the pixels thereon and the dummy regions with the circuit connection lines thereon from each other, each of the separated first regions with the pixel driving lines and the pixels thereon defining a thin film transistor board of the display panel assembly, and each of the separated dummy regions with the circuit connection lines thereon defining a driving circuit board of the display panel assembly; and connecting the driving circuit board with the circuit connection lines thereon to the thin film transistor board with the pixel driving lines and the pixels thereon. ### Claim 2 (depends on 1) The method of claim 1, wherein each of the thin film transistor boards with the pixel driving lines and the pixels thereon has a long side in a first direction, and has a short side in a second direction which intersects with the first direction. ### Claim 3 (depends on 2) The method of claim 2, wherein the dummy regions with the circuit connection lines thereon comprise: a plurality of second regions disposed between first regions adjacent in the second direction; and a plurality of third regions disposed between first regions adjacent in the first direction. ### Claim 4 (depends on 3) The method of claim 3, wherein the mother substrate comprises further defined thereon: a plurality of first cutting lines extending in the first direction, the first cutting lines defined on the mother substrate at a boundary between first regions and second regions adjacent in the second direction; and a plurality of second cutting lines extending in the second direction, the second cutting lines defined on the mother substrate at a boundary between first regions and third regions adjacent in the first direction, and the dividing of the mother substrate to separate the first regions and the dummy regions from each other comprises: cutting the mother substrate including the pixel driving lines, the pixels and the circuit connection lines formed thereon along the first cutting lines to separate the first regions with the pixel driving lines and the pixels thereon and the second regions with second region circuit connection lines thereon from each other; and cutting the mother substrate including the pixel driving lines, the pixels and the circuit connection lines formed thereon along the second cutting lines to separate the first regions with the pixel driving lines and the pixels thereon and the third regions with third region circuit connection lines thereon from each other. ### Claim 5 (depends on 3) The method of claim 3, wherein the forming of the plurality of the circuit connection lines on each of the dummy regions comprises forming second region circuit connection lines on a second region among the plurality of second regions, and the connecting of the driving element to the circuit connection lines comprises connecting the driving element to the second region circuit connection lines of the second region among the plurality of second regions to form the driving circuit board as a first printed circuit board. ### Claim 6 (depends on 5) The method of claim 5, wherein the connecting of the driving circuit board to the thin film transistor board comprises connecting the first printed circuit board to the thin film transistor board through a plurality of first flexible circuit boards on which first data driving chips are mounted. ### Claim 7 (depends on 6) The method of claim 6, wherein the first printed circuit board is connected to the long side of the thin film transistor board through the first flexible circuit boards. ### Claim 8 (depends on 7) The method of claim 7, wherein the driving element is connected to the first data driving chips mounted on the first flexible circuit boards through the second region circuit connection lines of the first printed circuit board, and a data driving unit comprising the first data driving chips is connected to the pixel driving lines of the thin film transistor board connected to the first printed circuit board. ### Claim 9 (depends on 8) The method of claim 8, wherein the pixel driving lines on the thin film transistor board of which the long side thereof is connected to the first printed circuit board comprise a plurality of data lines. ### Claim 10 (depends on 9) The method of claim 9, wherein the driving element comprises a timing controller and a power generation unit. ### Claim 11 (depends on 10) The method of claim 10, wherein the forming of the plurality of pixels which is connected to the pixel driving lines on each of the first regions forms an amorphous silicon type gate driving unit on each of the first regions at the same time. ### Claim 12 (depends on 10) The method of claim 10, wherein the forming of the plurality of circuit connection lines on each of the dummy regions further comprises forming third region circuit connection lines on a third region among the third regions to form a second printed circuit board. ### Claim 13 (depends on 12) The method of claim 12, wherein the connecting of the driving circuit board to the thin film transistor board substrate further comprises connecting the second printed circuit board to the thin film transistor board through a plurality of second flexible circuit boards on which second data driving chips are mounted. ### Claim 14 (depends on 13) The method of claim 13, wherein the second printed circuit board is connected to the short side of the thin film transistor board through the second flexible circuit boards. ### Claim 15 (depends on 14) The method of claim 14, wherein the pixel driving lines on the thin film transistor board of which the short side thereof is connected to the second printed circuit board further comprise a plurality of gate lines, wherein a gate driving unit comprising the second data driving chips is connected to each of: the third region circuit connection lines of the second printed circuit board, the second region circuit connection lines of the first printed circuit board, and the pixel driving lines of the thin film transistor board connected to the second printed circuit board. ### Claim 16 (depends on 1) The method of claim 1, wherein the forming of the pixel driving lines, the pixels and the circuit connection lines comprises a photolithography process. ### Claim 17 (depends on 1) The method of claim 1, further comprising: disposing a color filter board so as to be opposed to the thin film transistor board with the pixel driving lines and the pixels thereon; and disposing a liquid crystal layer between the thin film transistor board with the pixel driving lines and the pixels thereon and the color filter board.