# US 9,437,614 B1 · Dual-semiconductor complementary metal-oxide-semiconductor device

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- Number: US 9,437,614 B1
- Document ID: US9437614B1
- Status: Granted
- Kind: B1
- Application number: 14/858,964
- Filed: 2015-09-18
- Granted: 2016-09-06
- Earliest claimed: 2015-09-18
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Sanghoon Lee; Effendi Leobandung; Renee T. Mo; Yanning Sun
- Web page: https://patentgrep.com/patent/US9437614B1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/40: Crystalline structures
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 64/01326: {Aspects related to lithography, isolation or planarisation of the conductor}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10P 14/274: {using seed materials}
- H10P 14/3421: {Arsenides}
- H10P 14/3462: {Nanowires}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/751: {having composition variations in the channel regions}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/8325: {Silicon carbide}
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 86/01: Manufacture or treatment
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming an active device on a semiconductor wafer includes the steps of: forming a plurality of semiconductor fins on at least a portion of a semiconductor substrate; forming a dielectric layer on at least a portion of the semiconductor substrate, the dielectric layer filling gaps between adjacent fins; forming a plurality of gate structures on an upper surface of the dielectric layer; forming a channel region on the dielectric layer and under at least a portion of the gate structures, the channel region comprising a first crystalline semiconductor material; forming source and drain epitaxy regions on an upper surface of the dielectric layer and between adjacent gate structures, the source and rain regions being spaced laterally from one another; and replacing the channel region with a second crystalline semiconductor material after high-temperature processing used in fabricating the active device has been completed.

## Claims

### Claim 1

An active semiconductor device, comprising:
a plurality of semiconductor fins formed on at least a portion of a semiconductor substrate;
a first dielectric layer formed on at least a portion of an upper surface of the semiconductor substrate, the first dielectric layer filling gaps between adjacent fins;
a plurality of gate structures formed on an upper surface of the first dielectric layer;
a channel region formed on the upper surface of the first dielectric layer and under at least a portion of the gate structures, the channel region comprising a first crystalline semiconductor material, the channel region further comprising a second crystalline semiconductor material formed on at least a portion of the upper surface of the first dielectric layer and between the gate structures, the second crystalline semiconductor material encapsulating the first crystalline semiconductor material and filling openings formed between the fins, the channel region being channel region being formed after high-temperature processing used in fabricating the active semiconductor device has been completed; and
source and drain regions formed on the upper surface of the first dielectric layer and between adjacent gate structures, the source and rain regions being spaced laterally from one another.

### Claim 2 (depends on 1)

The device of claim 1, further comprising a second dielectric layer formed over at least a portion of an upper surface of said semiconductor device, an upper surface of the second dielectric layer being planarized to a height of an upper surface of said gate structures.

### Claim 3 (depends on 1)

The device of claim 1, wherein the second crystalline semiconductor material comprises a horizontally grown nanowire structure.

### Claim 4 (depends on 1)

The device of claim 1, wherein the second crystalline semiconductor material comprises a Group III-V material.

### Claim 5 (depends on 1)

The device of claim 1, further comprising insulating spacers formed on at least a portion of sidewalls of said gate structures, the insulating spacers electrically isolating the gate structures from the second crystalline semiconductor material.

### Claim 6 (depends on 1)

The device of claim 1, wherein each of at least a subset of said plurality of gate structures comprises a metal.

### Claim 7 (depends on 1)

The device of claim 1, wherein said first and second crystalline semiconductor materials are different relative to one another.