# US 9,437,613 B2 · Multiple VT in III-V FETs

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- Number: US 9,437,613 B2
- Document ID: US9437613B2
- Status: Granted
- Kind: B2
- Application number: 15/057,900
- Filed: 2016-03-01
- Published: 2016-06-23
- Granted: 2016-09-06
- Earliest claimed: 2014-12-22
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Josephine B. Chang; Isaac Lauer; Amlan Majumdar; Jeffrey W. Sleight
- Web page: https://patentgrep.com/patent/US9437613B2

## CPC

- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 30/502: {characterised by the stacked channels}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 30/674: {characterised by the active materials}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/221: {of FETs}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 62/852: being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 84/05: using Group III-V technology
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 86/01: Manufacture or treatment
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In one aspect, a method of forming a multiple VT device structure includes the steps of: forming an alternating series of channel and barrier layers as a stack having at least one first channel layer, at least one first barrier layer, and at least one second channel layer; defining at least one first and at least one second active area in the stack; selectively removing the at least one first channel/barrier layers from the at least one second active area, such that the at least one first channel layer and the at least one second channel layer are the top-most layers in the stack in the at least one first and the at least one second active areas, respectively, wherein the at least one first barrier layer is configured to confine charge carriers to the at least one first channel layer in the first active area.

## Claims

### Claim 1

A multiple VT device structure, comprising:
an alternating series of channel layers and barrier layers in a stack on a side of a BOX opposite a substrate, wherein the stack comprises at least one first channel layer present over at least one first barrier layer, and at least one second channel layer present below the at least one first barrier layer, wherein the at least one first channel layer comprises a first III-V material and the at least one second channel layer comprises a second III-V material, and wherein the first III-V material has a different electron affinity from the second III-V material;
at least one first active area and at least one second active area defined in the stack, wherein the at least one first channel layer is a top-most layer in the stack in the at least one first active area, and the at least one second channel layer is a top-most layer in the stack in the at least one second active area, wherein the at least one first barrier layer is configured to confine charge carriers to the at least one first channel layer in the first active area;
at least one first gate on the at least one first channel layer in the at least one first active area; and
at least one second gate on the at least one second channel layer in the at least one second active area,
wherein the at least one first channel layer serves as a channel of a first FET in the at least one first active area, and the at least one second channel layer serves as a channel of a second FET in the at least one second active area, and wherein the first FET has a different VT from the second FET based on the different electron affinity between the first III-V material and the second III-V material.

### Claim 2 (depends on 1)

The multiple VT device structure of claim 1, wherein the at least one first barrier layer comprises a wider band gap III-V material than the first III-V material.

### Claim 3 (depends on 1)

The multiple VT device structure of claim 1, wherein the at least one first gate and the at least one second gate each both comprise a gate dielectric, a gate metal layer on the gate dielectric, and a semiconductor gate layer on a side of the gate metal layer opposite the gate dielectric.

### Claim 4 (depends on 3)

The multiple VT device structure of claim 3, wherein the gate metal layer comprises a same gate metal in both the at least one first gate and the at least one second gate.

### Claim 5 (depends on 1)

The multiple VT device structure of claim 1, further comprising:
spacers on opposite sides of the at least one first gate and on opposite sides of the at least one second gate; and
raised source and drain regions on the at least one first channel layer on opposite sides of the at least one first gate, and on the at least one second channel layer on opposite sides of the at least one second gate.

### Claim 6 (depends on 5)

The multiple VT device structure of claim 5, further comprising:
contacts to the raised source and drain regions.

### Claim 7 (depends on 1)

The multiple VT device structure of claim 1, wherein the stack further comprises at least one second barrier layer below the at least one second channel layer and at least one third channel layer below the at least one second barrier layer, wherein the at least one third channel layer comprises a third III-V material, and wherein the third III-V material has a different electron affinity from both the first III-V material and the second III-V material.

### Claim 8 (depends on 7)

The multiple VT device structure of claim 7, further comprising:
at least one third active area defined in the stack, wherein the at least one third channel layer is a top-most layer in the stack in the at least one third active area, and wherein the at least one second barrier layer is configured to confine charge carriers to the at least one third channel layer in the third active area.

### Claim 9 (depends on 8)

The multiple VT device structure of claim 8, further comprising:
at least one third gate on the at least one third channel layer in the at least one third active area, wherein the at least one third channel layer serves as a channel of a third FET in the at least one third active area, and wherein the third FET has a different VT from both the first FET and the second FET based on the different electron affinity between the first III-V material, the second III-V material, and the third III-V material.