# US 9,437,612 B1 · Three-dimensional memory

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- Number: US 9,437,612 B1
- Document ID: US9437612B1
- Status: Granted
- Kind: B1
- Application number: 14/832,220
- Filed: 2015-08-21
- Granted: 2016-09-06
- Earliest claimed: 2015-08-21
- Assignees: Macronix International Co., Ltd.
- Applicants: MACRONIX International Co., Ltd.
- Inventors: Chih-Wei Lee; Cheng-Hsien Cheng; Shaw-Hung Ku; Wen-Pin Lu
- Web page: https://patentgrep.com/patent/US9437612B1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 30/689: {Vertical floating-gate IGFETs}
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/40: Crystalline structures
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10W 20/43: Layouts of interconnections
- H10W 20/4451: {Semiconductor materials, e.g. polysilicon}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A three-dimensional memory, which includes memory cell stacked structures. The memory cell stacked structures are stacked by a plurality of memory cell array structures and insulation layers alternatively, and each memory cell array structure includes word lines, active layers, composite layers and sources/drains. The word lines, the active layers and the composite layers extend along a Y direction. The active layers are disposed between the adjacent word lines. The composite layers are disposed between the adjacent word lines and the adjacent active layers, and each composite layer includes a first dielectric layer, a charge storage layer and a second dielectric layer in sequence from the active layers. The sources/drains are disposed in the active layers at equal intervals. A memory cell includes two adjacent sources/drains, the active layer between the two adjacent sources/drains, the first dielectric layer, the charge storage layer and the second dielectric layer on the active layer, and the word lines.

## Claims

### Claim 1

A three-dimensional memory, comprising:
memory cell stacked structures, stacked by a plurality of memory cell array structures and a plurality of insulation layers alternatively, and each memory cell array structure comprising:
a plurality of word lines, extending along a Y direction;
a plurality of active layers, extending along the Y direction and disposed between the adjacent word lines;
a plurality of composite layers, extending along the Y direction and disposed between the adjacent word lines and the adjacent active layers, wherein each composite layer comprises a first dielectric layer, a charge storage layer and a second dielectric layer in sequence from the active layer; and
a plurality of sources/drains, disposed in the active layers at equal intervals, wherein a memory cell comprises two adjacent sources/drains, the active layer between the two adjacent sources/drains, and the first dielectric layer, the charge storage layer and the second dielectric layer on the active layer, and the word lines.

### Claim 2 (depends on 1)

The three-dimensional memory according to claim 1, further comprising a plurality of conductive pillars, extending along a Z direction and electrically connected with the sources/drains in the memory cell stacked structures.

### Claim 3 (depends on 1)

The three-dimensional memory according to claim 1, further comprising a plurality of bit lines, extending along an X direction and electrically connected with the conductive pillars on the X direction.

### Claim 4 (depends on 3)

The three-dimensional memory according to claim 3, wherein the bit lines comprises polycrystalline silicon, doped polycrystalline silicon, metal silicide or metal.

### Claim 5 (depends on 1)

The three-dimensional memory according to claim 1, wherein the charge storage layers comprises silicon nitride, polycrystalline silicon or doped polycrystalline silicon, and the three-dimensional memory further comprises a plurality of isolation layers, disposed in the charge storage layers to isolate the charge storage layers of the adjacent memory cells.

### Claim 6 (depends on 1)

The three-dimensional memory according to claim 1, wherein the word lines and the active layers each comprise polycrystalline silicon or doped polycrystalline silicon.

### Claim 7 (depends on 1)

The three-dimensional memory according to claim 1, wherein the sources/drains and the conductive pillars comprise polycrystalline silicon, doped polycrystalline silicon, germanide, metal silicide or metal.

### Claim 8 (depends on 1)

The three-dimensional memory according to claim 1, wherein the first dielectric layers, the second dielectric layers and the insulation layers each comprises silicon oxide.

### Claim 9 (depends on 1)

The three-dimensional memory according to claim 1, wherein in each memory cell stacked structure, two adjacent memory cells share one word line, or share one active layer and sources/drains on the X direction.

### Claim 10 (depends on 1)

The three-dimensional memory according to claim 1, wherein in each memory cell stacked structure, a plurality of the memory cells are connected in series and share one word line on the Y direction.