# US 9,437,611 B1 · Semiconductor device and manufacturing method thereof

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- Number: US 9,437,611 B1
- Document ID: US9437611B1
- Status: Granted
- Kind: B1
- Application number: 14/629,537
- Filed: 2015-02-24
- Published: 2016-08-25
- Granted: 2016-09-06
- Earliest claimed: 2015-02-24
- Assignees: Macronix International Co., Ltd.
- Applicants: Macronix International Co., Ltd.
- Inventors: Erh-Kun Lai
- Web page: https://patentgrep.com/patent/US9437611B1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 62/40: Crystalline structures
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps. A bottom insulating layer is formed on a substrate. Two stacked structures are formed on the bottom insulating layer. Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers, a top insulating layer and a conductive mask layer. Each of the charge trapping structures includes a plurality of first dielectric layers and a plurality of second dielectric layers. Part of each of first dielectric layers is etched. Part of each of second dielectric layers is etched to expose part of the channel layer. A landing pad layer is formed on the conductive mask layer, the first dielectric layers and the second dielectric layers to connect the conductive mask layer and the channel layer.

## Claims

### Claim 1

A manufacturing method of a semiconductor device, comprising:
forming a bottom insulating layer on a substrate;
forming two stacked structures on the bottom insulating layer, wherein each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers, a top insulating layer and a conductive mask layer, the gate layers and the gate insulating layers are alternately disposed on the bottom insulating layer, the top insulating layer is disposed on the gate layers and the gate insulating layers, and the conductive mask layer is disposed on the top insulating layer;
forming a charge trapping structure and a channel layer on a lateral surface of each of the stacked structures and a top surface of the bottom insulating layer, wherein each of the charge trapping structures includes a plurality of first dielectric layers and a plurality of second dielectric layers;
etching part of each of first dielectric layers to expose part of each of the second dielectric layers;
etching part of each of second dielectric layers to expose part of the channel layer; and
forming a landing pad layer on the conductive mask layer, the first dielectric layers and the second dielectric layers to connect the conductive mask layer and the channel layer.

### Claim 2 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, wherein each of the stacked structures further includes an insulating mask layer disposed on the conductive mask layer, in the step of etching part of each first dielectric layer, the insulating mask layer is removed.

### Claim 3 (depends on 2)

The manufacturing method of the semiconductor device according to claim 2, wherein a material of each of the first dielectric layers and a material of the insulating mask layer are the same.

### Claim 4 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, wherein a material of the conductive mask layer, a material of the channel layer and a material of the landing pad layer are the same.

### Claim 5 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, wherein in the step of etching part of each of the first dielectric layers, the first dielectric layers are etched with different depths.

### Claim 6 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, wherein in the step of etching part of each of the first dielectric layers, two lateral walls of at least one of the second dielectric layers are partially exposed.

### Claim 7 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, wherein in the step of etching part of each of the second dielectric layers, the second dielectric layers are etched with different depths.

### Claim 8 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, further comprising:
filling a spaced insulating layer in a trench formed between the stacked structures;
wherein in the step of etching part of each of the second dielectric layers, part of the spaced insulating layer is also etched, such that a top of the channel layer is higher than tops of the first dielectric layers and tops of the second dielectric layer.

### Claim 9 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, wherein the step of etching part of each of the second dielectric layers is performed after the step of etching part of each of the first dielectric layers.

### Claim 10 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, wherein a material of each of the first dielectric layers is silicon nitride, and a material of each of the second dielectric layers is silicon oxide.

### Claim 11 (depends on 1)

The manufacturing method of the semiconductor device according to claim 1, wherein a material of each of the gate layers is P type doping polysilicon, and a material of each of the conductive mask layer, the channel layer and the landing pad layer is N type doping polysilicon.