# US 9,437,610 B2 · Three dimensional stacked nonvolatile semiconductor memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,610 B2 - Document ID: US9437610B2 - Status: Granted - Kind: B2 - Application number: 14/589,523 - Filed: 2015-01-05 - Published: 2015-04-30 - Granted: 2016-09-06 - Earliest claimed: 2008-04-23 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Kabushiki Kaisha Toshiba - Inventors: Hiroshi Maejima - Web page: https://patentgrep.com/patent/US9437610B2 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/10: characterised by the top-view layout - H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 43/40: characterised by the peripheral circuit region - H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. A source diffusion layer, which is common to the first and second blocks, is disposed in a semiconductor substrate, and a contact plug, which has a lower end connected to the source diffusion layer and an upper end connected to a source line disposed above at least three conductive layers, is interposed between the first and second blocks. ## Claims ### Claim 1 A semiconductor memory device comprising: a semiconductor substrate; and a memory cell array including first and second blocks disposed above a semiconductor substrate side by side in a first direction, the first block including a first memory string extending in a second direction perpendicular to the first direction and a second memory string extending in the second direction, the first memory string including a first word line and a first select gate arranged in the second direction, the second memory string including the first word line and a second select gate arranged in the second direction, the first select gate and the second select gate being arranged in the first direction, the second block including a third memory string extending in the second direction and a fourth memory string extending in the second direction, the third memory string including a second word line and a third select gate arranged in the second direction, the fourth memory string including the second word line and a fourth select gate arranged in the second direction, the third select gate and the fourth select gate being arranged in the first direction, the second select gate and the third select gate being connected electrically. ### Claim 2 (depends on 1) The device according to claim 1, wherein the first select gate and the fourth select gate are connected electrically. ### Claim 3 (depends on 1) The device according to claim 1, wherein the memory cell array further including a bit line extending in the first direction, the bit line connected electrically with the first to fourth memory strings. ### Claim 4 (depends on 3) The device according to claim 3, wherein the memory cell array further including a source layer being common to the first and second blocks, a contact plug extending in the second direction and electrically connected with the source layer, and a wire extending in the first direction and electrically connected with the contact plug. ### Claim 5 (depends on 4) The device according to claim 4, wherein the contact plug is disposed between the first block and the second block. ### Claim 6 (depends on 4) The device according to claim 4, wherein the bit line and the wire are disposed in a same level. ### Claim 7 (depends on 4) The device according to claim 4, wherein the source layer is N-type semiconductor layer. ### Claim 8 (depends on 1) The device according to claim 1, wherein the memory cell array further includes a P-channel transistor electrically connected with the first word line. ### Claim 9 (depends on 1) The device according to claim 1, wherein the memory cell array further includes third and fourth blocks disposed above a semiconductor substrate, the first to fourth blocks arranged in the first direction, the third block including a fifth memory string extending in the second direction and a sixth memory string extending in the second direction, the fifth memory string including a third word line and a fifth select gate arranged in the second direction, the sixth memory string including the third word line and a sixth select gate arranged in the second direction, the fifth select gate and the sixth select gate being arranged in the first direction, the fourth block including a seventh memory string extending in the second direction and an eighth memory string extending in the second direction, the seventh memory string including a fourth word line and a seventh select gate arranged in the second direction, the eighth memory string including the fourth word line and an eighth select gate arranged in the second direction, the seventh select gate and the eighth select gate being arranged in the first direction, the sixth select gate and the seventh select gate being connected electrically. ### Claim 10 (depends on 9) The device according to claim 9, wherein the memory cell array further includes a first interconnect portion of the first and second blocks disposed on one side of the memory cell array, and a second interconnect portion of the third and fourth blocks disposed on another side of the memory cell array. ### Claim 11 (depends on 10) The device according to claim 10, wherein the memory cell array further includes a bit line extending in the first direction, the bit line connected electrically with the first to eighth memory strings. ### Claim 12 (depends on 11) The device according to claim 11, wherein the memory cell array further includes a source layer being common to the first to fourth blocks, a first contact plug extending in the second direction and electrically connected with the source layer, and a wire extending in the first direction and electrically connected with the first contact plug. ### Claim 13 (depends on 12) The device according to claim 12, wherein the first contact plug is disposed between the first block and the second block. ### Claim 14 (depends on 12) The device according to claim 12, wherein the memory cell array further includes a second contact plug extending in the second direction and electrically connected with the source layer and the wire. ### Claim 15 (depends on 14) The device according to claim 14, wherein the first contact plug is disposed between the first block and the second block, the second contact plug being disposed between the third block and the fourth block. ### Claim 16 (depends on 14) The device according to claim 14, wherein the bit line and the wire are disposed in a same level. ### Claim 17 (depends on 14) The device according to claim 14, wherein the source layer is N-type semiconductor layer.