# US 9,437,609 B2 · Vertical channel-type 3D semiconductor memory device and method for manufacturing the same

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- Number: US 9,437,609 B2
- Document ID: US9437609B2
- Status: Granted
- Kind: B2
- Application number: 14/581,990
- Filed: 2014-12-23
- Published: 2015-06-25
- Granted: 2016-09-06
- Earliest claimed: 2012-12-13
- Assignees: Institute of Microelectronics, Chinese Academy of Sciences
- Applicants: Institute of Microelectronics, Chinese Academy of Sciences
- Inventors: Zongliang Huo; Ming Liu
- Web page: https://patentgrep.com/patent/US9437609B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/10: characterised by the top-view layout
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 43/10: characterised by the top-view layout
- H10B 43/35: with cell select transistors, e.g. NAND
- H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling}
- H10D 30/689: {Vertical floating-gate IGFETs}
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/40: Crystalline structures
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 62/852: being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3421: {Arsenides}
- H10P 14/3454: {Amorphous}
- H10P 14/3456: {Polycrystalline}
- H10P 14/69392: {the material containing hafnium, e.g. HfO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/264: {by chemical means}
- H10P 50/283: {by chemical means}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- H10P 14/3802: {Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A vertical channel-type 3D semiconductor memory device and a method for manufacturing the same are disclosed. In one aspect, the device includes a multi-layer film formed by depositing alternating layers of insulation and an electrode material on a substrate. The device also includes through-holes formed by etching the film to the substrate. The device also includes gate stacks formed by depositing barrier storage and a tunnel layers in sequence on inner walls of the through-holes. The device also includes hollow channels formed by depositing a channel material on the tunnel layer. The device also includes drains for bit-line connection in top portions of the hollow channels. The device also includes sources formed in contact regions between through-holes and the substrate in bottom portions of the hollow channels.

## Claims

### Claim 1

A vertical channel-type 3D semiconductor memory device, comprising:
a substrate;
a multi-layer film formed by depositing alternating layers of at least one insulating layer and at least one electrode material layer on the substrate;
a plurality of through-holes, which define respective channel regions, formed by etching the multi-layer film to the substrate;
a plurality of gate stacks, each formed by depositing a barrier layer, a storage layer, and a tunnel layer in sequence on an inner wall of a respective one of the plurality of through-holes;
a plurality of hollow channels, each formed by depositing and incompletely filling a channel material on a surface of the tunnel layer of a respective one of the plurality of gate stacks;
a plurality of drains, each formed in a contact hole region for bit-line connection in a top portion of a respective one of the plurality of hollow channels; and
a plurality of sources, each formed in a contact region between a respective one of the plurality of through-holes and the substrate in a bottom portion of a respective one of the plurality of hollow channels.

### Claim 2 (depends on 1)

The device of claim 1, wherein each of the plurality of hollow channels has a column, annular, or strip shape, and/or wherein the channel material is selected from the group consisting of polysilicon, amorphous silicon, Ge—Si, Ge, GaAs, and InGaAs.

### Claim 3 (depends on 2)

The device of claim 2; wherein each of the plurality of hollow channels is formed by depositing a polysilicon film directly on the surface of a respective one of the tunnel layers.

### Claim 4 (depends on 2)

The device of claim 2, wherein each of the plurality of hollow channels is formed by depositing an amorphous silicon film on the surface of a respective one of the respective tunnel layers followed by high-temperature annealing.

### Claim 5 (depends on 1)

The device of claim 1, wherein each of the plurality of gate stacks is a charge capturing-type memory gate stack based on separate charge storage or a floating gate-type memory gate stack based on a continuous storage medium.

### Claim 6 (depends on 5)

The device of claim 5, wherein the charge capturing-type memory gate stack comprises:
a tunnel layer;
a separate dielectric storage layer; and
a barrier layer.

### Claim 7 (depends on 6)

The device of claim 6, wherein the separate dielectric storage layer comprises SiN or a high-K dielectric material of HfO.

### Claim 8 (depends on 5)

The device of claim 5, wherein the floating gate-type memory gate stack comprises:
a tunnel layer;
a storage layer; and
a barrier layer.

### Claim 9 (depends on 8)

The device of claim 8, wherein the storage layer comprises polysilicon, metal, or a combination of polysilicon and metal.