# US 9,437,604 B2 · Methods and apparatuses having strings of memory cells including a metal source

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- Number: US 9,437,604 B2
- Document ID: US9437604B2
- Status: Granted
- Kind: B2
- Application number: 14/069,553
- Filed: 2013-11-01
- Published: 2015-05-07
- Granted: 2016-09-06
- Earliest claimed: 2013-11-01
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Zhenyu Lu; Roger W. Lindsay; Andrew Bicksler; Yongjun J Hu; Haitao Liu
- Web page: https://patentgrep.com/patent/US9437604B2

## CPC

- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods for forming a string of memory cells, an apparatus having a string of memory cells, and a system are disclosed. A method for forming the string of memory cells comprises forming a metal silicide source material over a substrate. The metal silicide source material is doped. A vertical string of memory cells is formed over the metal silicide source material. A semiconductor material is formed vertically and adjacent to the vertical string of memory cells and coupled to the metal silicide source material.

## Claims

### Claim 1

A method comprising:
forming a metal silicide source layer over and in contact with a substrate;
doping the metal silicide source layer;
forming a capping material on the doped metal silicide source layer;
forming a select gate material on the capping material; and
forming a vertical string of floating gate memory cells on the select gate material and extending vertically from the doped metal silicide source layer after forming the metal silicide source layer over the substrate, the vertical string of memory cells including a pillar of semiconductor channel material formed on and extending vertically from and in contact with the doped metal silicide source layer at an ohmic contact, wherein the pillar of semiconductor channel material is not doped.

### Claim 2 (depends on 1)

The method of claim 1 wherein forming the string of memory cells comprises:
forming alternating levels of control gate material and insulator material over the select gate material;
forming an opening through the alternating levels of control gate material and insulator material, the select gate material, and the capping material, the opening comprising recesses formed on sidewalls of the opening in the control gate material;
forming a dielectric material over the recesses and the sidewalls of the opening of the alternating levels of control gate material and insulator material;
forming charge storage structures in the recesses;
forming a tunnel dielectric material over the charge storage structures and the sidewalls of the opening of the select gate material; and
forming the channel material in the opening such that the channel material contacts the doped metal silicide source layer.

### Claim 3 (depends on 2)

The method of claim 2 and further comprising forming a nitride hard mask over the alternating levels of control gate material and insulator material.

### Claim 4 (depends on 2)

The method of claim 2 wherein the dielectric material comprises an oxide-nitride-oxide (ONO) material.

### Claim 5 (depends on 2)

The method of claim 2 wherein the tunnel dielectric material and the insulator material comprise an oxide material.

### Claim 6 (depends on 2)

The method of claim 2 wherein the select gate material, the control gate material, the charge storage structures, and the channel material comprise a polysilicon.

### Claim 7 (depends on 2)

The method of claim 2 and further comprising forming an etch stop material between the select gate material and the alternating levels of control gate material and insulator material.

### Claim 8 (depends on 1)

The method of claim 1 and further comprising forming an oxide between the substrate and the doped metal silicide source layer.

### Claim 9 (depends on 1)

The method of claim 1 and further comprising forming a polysilicon material between the substrate and the doped metal silicide source layer.

### Claim 10 (depends on 1)

The method of claim 1 wherein the metal silicide source layer is one of: tungsten silicide (WSix), tantalum silicide (TaSix), molybdenum silicide (MoSix), or refractory metal silicides.

### Claim 11 (depends on 10)

The method of claim 10 wherein “x” ratio is in a range of 1.0 to 4.0.

### Claim 12 (depends on 1)

The method of claim 1 wherein the capping material comprises one of an oxide or a polysilicon material.

### Claim 13

A method comprising:
forming metal silicide source material onto a substrate;
forming an oxide material over the metal silicide source material;
doping the metal silicide source material;
forming a polysilicon select gate material over the oxide material; and
forming a string of floating gate memory cells over the polysilicon select gate material, the string of floating gate memory cells including undoped semiconductor channel material that extends through the polysilicon select gate material and the oxide material to contact the doped metal silicide source material.

### Claim 14 (depends on 13)

The method of claim 13 wherein doping the metal silicide source material comprises doping the metal silicide source material with one of arsenic, boron, phosphorus, or gallium.

### Claim 15 (depends on 13)

The method of claim 13 wherein doping the metal silicide source material comprises one of: doping the metal silicide material with arsenic or phosphorus to an n-type conductive material or doping the metal silicide source material with boron or gallium to create a p-type conductive material.

### Claim 16

A method comprising:
forming metal silicide source material onto a substrate;
forming a capping material over the metal silicide source material;
doping the metal silicide source material;
forming a select gate material over the capping material; and
forming a vertical string of floating gate memory cells over the select gate material, in a plurality of alternating levels of control gate material and insulator material, wherein forming the vertical string of memory cells comprises forming a vertical undoped semiconductor material coupled to the doped metal silicide source material and adjacent to the select gate material, wherein the floating gates of the vertical string of memory cells and the select gate material are insulated from the vertical undoped semiconductor material by a tunnel dielectric material.

### Claim 17 (depends on 16)

The method of claim 16 wherein forming the vertical string of memory cells comprises:
forming a recess in each level of control gate material;
lining the recess with a dielectric material; and
filling the lined recess with a floating gate material.

### Claim 18 (depends on 16)

The method of claim 16 wherein the insulator material and the tunnel dielectric material comprise an oxide material.

### Claim 19 (depends on 16)

The method of claim 16 wherein forming the vertical undoped semiconductor material coupled to the doped metal silicide source material comprises forming an ohmic contact between the vertical undoped semiconductor material and the doped metal silicide source material.