# US 9,437,602 B2 · Temperature compensation method for high-density floating-gate memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,602 B2 - Document ID: US9437602B2 - Status: Granted - Kind: B2 - Application number: 14/362,256 - Filed: 2012-11-27 - Published: 2015-01-08 - Granted: 2016-09-06 - Earliest claimed: 2011-12-02 - Assignees: Board of Trustees of Michigan State University - Applicants: Board of Trustees of Michigan State University - Inventors: Shantanu Chakrabartty; Ming Gu; Chenling Huang - Web page: https://patentgrep.com/patent/US9437602B2 ## CPC - H10B 41/40: characterised by the peripheral circuit region - G11C 7/04: with means for avoiding disturbances due to temperature effects - G11C 16/0408: {comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence)} - G11C 16/0441: {comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates} - G11C 27/005: {with non-volatile charge storage, e.g. on floating gate or MNOS} - G11C 27/028: {Current mode circuits, e.g. switched current memories} - H10D 1/68: Capacitors having no potential barriers - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10D 84/813: {Combinations of field-effect devices and capacitor only} - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A temperature compensation technique is provided for a non-volatile memory arrangement. The memory arrangement includes: a memory circuit (12) having a floating gate transistor (P3) operating in weak-inversion mode and a varactor (Cv) with a terminal electrically coupled to a gate node of the floating gate transistor; a first current reference circuit (14) having a floating gate transistor (PI); a second current reference circuit (16) having a floating gate transistor (P2); and a control module (18) configured to selectively receive a reference current (I1, I2) from a drain of the floating gate transistor in each of the first and second current reference circuits. The control module operates to determine a ratio between the reference currents received from the first and second current reference circuits, generate a tuning voltage (Vx) in accordance with the ratio between the reference currents and apply the tuning voltage to the varactor in the memory circuit. ## Claims ### Claim 1 A non-volatile memory arrangement, comprising: a first memory circuit having a floating gate transistor with a gate node and operating in weak-inversion mode, and a varactor with first terminal electrically coupled to the gate node of the floating gate transistor; and a control module electrically coupled to a second terminal of the varactor and operable to tune a voltage applied to the varactor, thereby compensating for temperature changes, wherein the first memory circuit further includes a tunneling capacitor coupled electrically to the gate node of the floating gate transistor and a control-gate capacitor coupled electrically to the gate node of the floating gate transistor, wherein the tunneling capacitor configured to receive an injection current for the first memory circuit. ### Claim 2 (depends on 1) The non-volatile memory arrangement of claim 1 wherein the varactor is further defined as a metal-oxide semiconductor capacitor operating in accumulation mode. ### Claim 3 A non-volatile memory arrangement, comprising: a first memory circuit having a floating gate transistor with a gate node and operating in weak-inversion mode, and a varactor with first terminal electrically coupled to the gate node of the floating gate transistor; a first current reference circuit and a second current reference circuit, the first and second current reference circuit each having a floating gate transistor operating in a weak-inversion mode and a varactor having a first terminal electrically coupled to a gate node of the floating gate transistor; and a control module electrically coupled to a second terminal of the varactor and operable to tune a voltage applied to the varactor, thereby compensating for temperature changes. ### Claim 4 (depends on 3) The non-volatile memory arrangement of claim 3 wherein the control module is configured to receive a reference current from a drain of the floating gate transistor in each of the first and second current reference circuits, the control module operates to selectively determine a ratio between the reference currents received from the first and second current reference circuits and determine a tuning voltage in accordance with the ratio between the reference currents. ### Claim 5 (depends on 4) The non-volatile memory arrangement of claim 4 wherein the control module applies the tuning voltage to a second terminal of the varactor in the first memory circuit. ### Claim 6 (depends on 5) The non-volatile memory arrangement of claim 5 wherein the control module applies the tuning voltage to a first terminal of the varactor in each of the first and second current reference circuits. ### Claim 7 (depends on 4) The non-volatile memory arrangement of claim 4 further comprises a second memory circuit having a floating gate transistor operating in weak-inversion mode and a varactor with a first terminal electrically coupled to a gate node of the floating gate transistor, wherein the control module applies the tuning voltage to a second terminal of the varactor in the second memory circuit. ### Claim 8 A non-volatile memory arrangement, comprising: a first memory circuit having a floating gate transistor with a gate node and operating in weak-inversion mode, and a varactor with a first terminal electrically coupled to the gate node of the floating gate transistor; a first current reference circuit having a floating gate transistor operating in a weak-inversion mode and a varactor with a first terminal electrically coupled to a gate node of the floating gate transistor; a second current reference circuit having a floating gate transistor operating in a weak-inversion mode and a varactor with a first terminal electrically coupled to a gate node of the floating gate transistor; and a control module configured to selectively receive a reference current from a drain of the floating gate transistor in each of the first and second current reference circuits and determine a ratio between the reference currents received from the first and second current reference circuits, the control module further operates to generate a tuning voltage that maintains the ratio between the reference currents constant and applies the tuning voltage to a second terminal of the varactor in the first memory circuit. ### Claim 9 (depends on 8) The non-volatile memory arrangement of claim 8 wherein the control module further operates to adjust the tuning voltage applied to the varactor of the first memory circuit. ### Claim 10 (depends on 8) The non-volatile memory arrangement of claim 8 wherein the control module applies the tuning voltage to a first terminal of the varactor in each of the first and second current reference circuits. ### Claim 11 (depends on 8) The non-volatile memory arrangement of claim 8 wherein the first memory circuit further includes a tunneling capacitor coupled electrically to the gate node of the floating gate transistor and a control-gate capacitor coupled electrically to the gate node of the floating gate transistor, wherein the tunneling capacitor configured to receive an injection current for the first memory circuit. ### Claim 12 (depends on 8) The non-volatile memory arrangement of claim 8 wherein the varactor of the first memory circuit is further defined as a metal-oxide semiconductor capacitor operating in accumulation mode. ### Claim 13 A non-volatile memory arrangement comprising: an array of memory circuits, each memory circuit having a floating gate transistor operating in weak-inversion mode and a varactor with a first terminal electrically coupled to a gate node of the floating gate transistor; a first current reference circuit having a floating gate transistor operating in a weak-inversion mode and a varactor with a first terminal electrically coupled to a gate node of the floating gate transistor; a second current reference circuit having a floating gate transistor operating in a weak-inversion mode and a varactor with a first terminal electrically coupled to a gate node of the floating gate transistor; and a control module configured to selectively receive a reference current from a drain of the floating gate transistor in each of the first and second current reference circuits and determine a ratio between the reference currents received from the first and second current reference circuits, the control module further operates to generate a tuning voltage in accordance with the ratio between the reference currents and applies the tuning voltage to the varactor of each memory circuit in the array of memory circuits. ### Claim 14 (depends on 13) The non-volatile memory arrangement of claim 13 wherein the control module applies the tuning voltage to a first terminal of the varactor in each of the first and second current reference circuits. ### Claim 15 (depends on 13) The non-volatile memory arrangement of claim 13 wherein each memory circuit further includes a tunneling capacitor coupled electrically to the gate node of the floating gate transistor and a control-gate capacitor coupled electrically to the gate node of the floating gate transistor, wherein the tunneling capacitor configured to receive an injection current for the memory circuit. ### Claim 16 (depends on 13) The non-volatile memory arrangement of claim 13 wherein the varactor for a given memory circuit in the array of memory circuits is further defined as a metal-oxide semiconductor capacitor operating in accumulation mode.