# US 9,437,600 B2 · Flash memory structure and method of making the same

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- Number: US 9,437,600 B2
- Document ID: US9437600B2
- Status: Granted
- Kind: B2
- Application number: 14/685,614
- Filed: 2015-04-14
- Published: 2016-03-10
- Granted: 2016-09-06
- Earliest claimed: 2014-09-04
- Assignees: Powerchip Technology Corporation
- Applicants: Powerchip Technology Corporation
- Inventors: Cheng-Yuan Hsu; Tzung-Hua Ying
- Web page: https://patentgrep.com/patent/US9437600B2

## CPC

- H10B 41/30: characterised by the memory core region
- G11C 16/0433: {comprising cells containing a single floating gate transistor and one or more separate select transistors}
- G11C 16/10: Programming or data input circuits
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/68: Floating-gate IGFETs
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10D 64/013: {of electrodes having a conductor capacitively coupled to a semiconductor by an insulator}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10P 50/264: {by chemical means}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of making a flash memory includes providing a substrate. Then, a first insulating layer, a first conductive layer and a second insulating layer are formed to cover the substrate. Later, a first trench is formed in the first conductive layer and the second insulating layer. After that, a second conductive layer and a mask layer are formed to cover the second insulating layer, and the second conductive layer fills up the first trench. Then, the mask layer are patterned to form patterned mask layers. Subsequently, a spacer is formed on the sidewall of the patterned mask layer. Then, an etching process is carried out by using the patterned mask layers and the spacer as a mask so as to form a first gate structure and a second gate structure.

## Claims

### Claim 1

A flash memory structure, comprising:
a first gate structure;
a second gate structure; and
a source and a drain respectively disposed at one side of said first gate structure and at the other side of said second gate structure;
wherein said first gate structure and said second gate structure are formed on a substrate next to each other, and there is a gap disposed between said first gate structure and said second gate structure;
said first gate structure and said second gate structure respectively comprise: a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a mask layer and a spacer to cover the sidewall of said mask layer,
wherein said spacer serves as an etching mask and said gap is self-alignment defined by using said spacer;
wherein said first conductive layer and said second insulating layer of said first gate structure have a trench and said second conductive layer extends to said trench to connect said first conductive layer, and said first gate structure serves as a select gate and said second gate structure serves as a control gate and a floating gate;
wherein there is no implanted area in said substrate between said first gate structure and said second gate structure.

### Claim 2 (depends on 1)

The flash memory structure of claim 1, wherein said spacer extends downwards to cover the sidewall of said second conductive layer.

### Claim 3 (depends on 1)

The flash memory structure of claim 1, wherein said spacer extends downwards to cover the sidewall of said second conductive layer and of said second insulating layer.

### Claim 4 (depends on 1)

The flash memory structure of claim 1, wherein said spacer extends downwards to cover the sidewall of said second conductive layer, of said second insulating layer and said first conductive layer.

### Claim 5 (depends on 1)

The flash memory structure of claim 1, wherein said gap disposed between said first gate structure and said second gate structure is 50 to 400 Å.