# US 9,437,599 B2 · Nonvolatile semiconductor memory device and method of manufacturing the same

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- Number: US 9,437,599 B2
- Document ID: US9437599B2
- Status: Granted
- Kind: B2
- Application number: 14/635,287
- Filed: 2015-03-02
- Published: 2016-02-18
- Granted: 2016-09-06
- Earliest claimed: 2014-08-12
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Kabushiki Kaisha Toshiba
- Inventors: Koichi Matsuno
- Web page: https://patentgrep.com/patent/US9437599B2

## CPC

- H10B 41/30: characterised by the memory core region
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/68: Floating-gate IGFETs
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/681: {having a compositional variation, e.g. multilayered}
- H10D 64/687: {having cavities, e.g. porous gate dielectrics having gasses therein}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 70/27: {during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers}
- H10P 70/273: {the processing being a delineation of conductive layers, e.g. by RIE}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

According to an embodiment, a nonvolatile semiconductor memory device comprises: a semiconductor layer; a first gate insulating film; a plurality of floating gate electrodes; a second gate insulating film; a plurality of control gate electrodes; and an upper insulating film. The semiconductor layer is provided on a substrate and extends in a first direction. The floating gate electrode is formed on the semiconductor layer via the first gate insulating film. The control gate electrode faces the upper surface of the floating gate electrode via the second gate insulating film. Moreover, the control gate electrode extends in a second direction intersecting the first direction. The upper insulating film is formed on an upper portion of the plurality of control gate electrodes. Moreover, a height of an upper surface of the upper insulating film changes along the second direction.

## Claims

### Claim 1

A nonvolatile semiconductor memory device, comprising:
a semiconductor layer provided on a substrate and extending in a first direction;
a first gate insulating film formed on the semiconductor layer;
a plurality of floating gate electrodes formed on the first gate insulating film along the semiconductor layer;
a second gate insulating film formed on an upper surface of the floating gate electrode;
a plurality of control gate electrodes respectively facing the upper surfaces of the plurality of floating gate electrodes via the second gate insulating film, and extending in a second direction intersecting the first direction; and
an upper insulating film formed on an upper portion of the plurality of control gate electrodes,
a height of an upper surface of the upper insulating film being a first height at a first position in the second direction and being a second height lower than the first height at a second position different from the first position in the second direction;
the upper insulating film comprising:
a plurality of first insulating layers formed in the second direction, each extending in the first direction; and
a second insulating layer positioned on the upper surface of the plurality of the first insulating layers and between the plurality of first insulating layers,
the first insulating layer being positioned at the first position in the second direction and a height of the upper surface of the second insulating layer being the first height at the first position, and
a portion between the first insulating layers being positioned at the second position in the second direction and a height of the upper surface of the second insulating layer being the second height at the second position.

### Claim 2 (depends on 1)

The nonvolatile semiconductor memory device according to claim 1, further comprising:
a silicon nitride film formed on an upper portion of the upper insulating film, wherein
a height of the silicon nitride film is a third height at the first position and a fourth height lower than the third height at the second position.

### Claim 3 (depends on 1)

The nonvolatile semiconductor memory device according to claim 1, wherein
the control gate electrode includes a layer configured from tungsten.

### Claim 4 (depends on 1)

The nonvolatile semiconductor memory device according to claim 1, further comprising:
a plurality of the semiconductor layers formed in the second direction; and
an element isolation film formed between the plurality of semiconductor layers, wherein
a height of an upper surface of the element isolation film is lower than a height of an upper surface of the first gate insulating film.

### Claim 5 (depends on 1)

The nonvolatile semiconductor memory device according to claim 1, wherein
the height of the upper surface of the upper insulating film is the first height at a position which is the first position in the second direction and which is between the plurality of the control electrodes in the first direction, and
the height of the upper surface of the upper insulating film is the second height at a position which is the second position in the second direction and which is between the plurality of the control electrodes in the first direction.