# US 9,437,597 B2 · Static random access memory (SRAM) device with FinFET transistors

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- Number: US 9,437,597 B2
- Document ID: US9437597B2
- Status: Granted
- Kind: B2
- Application number: 15/013,902
- Filed: 2016-02-02
- Published: 2016-06-02
- Granted: 2016-09-06
- Earliest claimed: 2014-04-25
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation
- Inventors: Mieno Fumitake
- Web page: https://patentgrep.com/patent/US9437597B2

## CPC

- H10B 10/12: {comprising a MOSFET load element}
- H10B 10/00: Static random access memory [SRAM] devices
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/853: {comprising FinFETs}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10P 50/268: {of silicon-containing layers}
- H10P 50/667: {by liquid etching only}
- H10P 50/73: {using masks for insulating materials}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a static memory cell and fabrication method. A first fin part is formed on a semiconductor substrate. An isolation layer is formed to cover a lower portion of sidewalls of the first fin part. A first dummy gate structure is formed across the first fin part. A dielectric layer is formed on the isolation layer. A mask layer is formed on the dielectric layer with a first opening to expose the top surface of the first dummy gate structure. The first dummy gate structure is removed through the first opening to form a first trench exposing the first fin part. A portion of the isolation layer is removed through the first opening to form a second trench exposing a portion of sidewalls of the first fin part below the top surface of the isolation layer. A first gate structure is formed by filling up the first and the second trenches.

## Claims

### Claim 1

A static memory cell, comprising:
a semiconductor substrate having a first region and a second region;
a first fin structure extending from the semiconductor substrate in the first region;
a second fin structure extending from the semiconductor substrate in the second region;
an isolation layer on the semiconductor substrate exposed by the first fin structure and the second fin structure;
a first gate structure disposed across a length of the first fin structure, wherein the first gate structure covers a height of the first fin structure above a top surface of the isolation layer and covers a depth of the first fin structure below the top surface of the isolation layer; and
a second gate structure disposed across a length of the second fin structure, wherein the second gate structure covers a height of the first fin structure above a top surface of the isolation layer and does not cover a depth of the second fin structure below the top surface of the isolation layer.

### Claim 2 (depends on 1)

The static memory cell of claim 1, wherein:
a ratio between a height of the first fin part above the top surface of the isolation layer and a depth of the second trench ranges approximately from 0.1 to 1.

### Claim 3 (depends on 1)

The static memory cell of claim 1, further including:
a first sidewall spacer disposed on sidewalls of the first gate structure, a second sidewall spacer disposed on sidewalls of the second gate structure, wherein:
the first sidewall spacer and the second sidewall spacer are disposed on the top surface of the isolation layer.

### Claim 4 (depends on 1)

The static memory cell of claim 1, wherein:
the first gate structure includes a first gate dielectric layer located on the first fin part, and a first gate electrode located on the first gate dielectric layer to fill up the first trench and the second trench; and
the second gate structure includes a second gate dielectric layer located on the second fin part, and a second gate electrode located on the second gate dielectric layer to fill up the third trench.

### Claim 5 (depends on 4)

The static memory cell of claim 4, wherein:
the first gate structure further includes a first work function layer located between the first gate electrode and the first gate dielectric layer; and
the second gate structure further includes a second work function layer located between the second gate electrode and the second gate dielectric layer.