# US 9,437,593 B2 · Silicided semiconductor structure and method of forming the same

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- Number: US 9,437,593 B2
- Document ID: US9437593B2
- Status: Granted
- Kind: B2
- Application number: 14/488,020
- Filed: 2014-09-16
- Published: 2015-01-01
- Granted: 2016-09-06
- Earliest claimed: 2009-02-03
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Jiang Yan; Henning Haffner; Frank Huebinger; Sun-Oo Kim; Richard Lindsay; Klaus Schruefer
- Web page: https://patentgrep.com/patent/US9437593B2

## CPC

- H10D 84/40: characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 64/666: {the conductor further comprising additional layers}
- H10W 20/493: {Fuses, i.e. interconnections changeable from conductive to non-conductive}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A preferred embodiment includes a method of manufacturing a fuse element that includes forming a polysilicon layer over a semiconductor structure, doping the polysilicon layer with carbon or nitrogen, depositing a metal over the polysilicon layer; and annealing the metal and polysilicon layer to form a silicide in an upper portion of the polysilicon layer.

## Claims

### Claim 1

A semiconductor device comprising:
a transistor at a surface of a semiconductor body, the transistor comprising:
a first source/drain region;
a second source/drain region;
a channel region between the first and second source/drain regions;
a gate dielectric overlying the channel region; and
a gate overlying the gate dielectric, the gate comprising a first silicide layer and a metal layer disposed between the gate dielectric and the first silicide layer, the first silicide layer having a first thickness; and
a fuse element disposed at the surface of the semiconductor body, the fuse element comprising a dielectric layer, a polysilicon layer and a second silicide layer having a second thickness that is smaller than the first thickness, wherein the fuse element does not comprise a metal layer having a metal material that is the same as a metal material of the metal layer of the transistor.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the ratio between the first thickness and the second thickness is about 1.1 to 1.5.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the polysilicon layer of the fuse element is doped with carbon or nitrogen.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the gate of the transistor further comprises a polysilicon layer between the gate dielectric and the first silicide layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the fuse element overlies an isolation structure, the isolation structure abutting the first source/drain region.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the fuse element is partially recessed within the isolation structure.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the polysilicon layer of the fuse element is disposed on and physically contacts the dielectric layer.

### Claim 8

A semiconductor device comprising:
a transistor at a surface of a semiconductor body, the transistor comprising:
a first source/drain region;
a second source/drain region;
a channel region between the first and second source/drain regions;
a gate dielectric overlying the channel region; and
a gate overlying the gate dielectric, the gate comprising a metal layer, a polysilicon layer, and a silicide layer, the silicide layer having a first thickness; and
a fuse element disposed at the surface of the semiconductor body, the fuse element comprising a polysilicon layer and a silicide layer having a second thickness that is smaller than the first thickness, wherein the fuse element further comprises a dielectric layer between the polysilicon layer and semiconductor body, and wherein a dielectric material of the dielectric layer of the fuse element and a dielectric material of the gate dielectric are the same, wherein the fuse element does not comprise a metal layer having a metal material that is the same as a metal material of the metal layer of the transistor.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the ratio between the first thickness and the second thickness is about 1.1 to 1.5.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the polysilicon layer of the fuse element is doped with carbon or nitrogen.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein the fuse element overlies an isolation structure, the isolation structure abutting the first source/drain region.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein a silicide material of the silicide layer of the fuse element and a silicide material of the silicide layer of the transistor are the same.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein the fuse element is partially recessed within a isolation structure.

### Claim 14

A semiconductor device comprising:
a transistor disposed at a first region of a surface of a semiconductor body, the transistor comprising:
a first source/drain region;
a second source/drain region;
a channel region between the first and second source/drain regions;
a gate dielectric overlying the channel region; and
a gate overlying the gate dielectric, the gate comprising a first silicide layer and a metal layer disposed between the gate dielectric and the first silicide layer, the first silicide layer having a first thickness; and
a fuse element disposed at a second region of the surface of the semiconductor body, the fuse element comprising:
an isolation structure located in the semiconductor body;
a dielectric layer overlying the isolation structure;
a polysilicon layer overlying the dielectric layer, wherein the polysilicon layer of the fuse element is disposed over and physically contacts the dielectric layer; and
a second silicide layer overlying the polysilicon layer, wherein the fuse element is located adjacent to the transistor such that the isolation structure abuts the first source/drain region, wherein the fuse element does not comprise a metal layer having a metal material that is the same as a metal material of the metal layer of the transistor.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the second silicide layer is disposed over and physically contacts the polysilicon layer.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, wherein the polysilicon layer of the fuse element is doped with carbon.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, wherein the polysilicon layer of the fuse element is doped with nitrogen.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, wherein the second silicide layer has a second thickness that is smaller than the first thickness.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the ratio between the first thickness and the second thickness is about 1.1 to 1.5.