# US 9,437,591 B1 · Cross-domain electrostatic discharge protection device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,591 B1 - Document ID: US9437591B1 - Status: Granted - Kind: B1 - Application number: 14/849,054 - Filed: 2015-09-09 - Granted: 2016-09-06 - Earliest claimed: 2015-09-09 - Assignees: Vanguard International Semiconductor Corporation - Applicants: Vanguard International Semiconductor Corporation - Inventors: Karuna Nidhi; Federico Agustin Altolaguirre; Ming-Dou Ker; Geeng-Lih Lin - Web page: https://patentgrep.com/patent/US9437591B1 ## CPC - H10D 89/713: {including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices} - H10D 1/47: Resistors having no potential barriers - H10D 1/68: Capacitors having no potential barriers - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 84/403: {Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors} - H10D 84/85: Complementary IGFETs, e.g. CMOS - H10D 89/811: {using FETs as protective elements} - H10D 89/911: {using passive elements as protective elements} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A cross-domain electrostatic protection device having four embedded silicon controlled rectifiers (a QSCR structure) embedded in a single cell. Two grounded-gate NMOS transistors are embedded into the cross-domain electrostatic protection device for reducing trigger voltage of the QSCR structure. Furthermore, an external trigger circuit and a bias circuit are applied to the cross-domain electrostatic protection device to reduce trigger voltage of the QSCR structure and leakage current. ## Claims ### Claim 1 A cross-domain electrostatic discharge protection device, comprising: a deep n-well formed in a substrate; a first p-well and a second p-well formed in the deep n-well; a first n-well formed in the deep n-well and between the first p-well and the second p-well, the first n-well contacting the first p-well and the second p-well; a first p-type doped region and a second p-type doped region formed in the first n-well; a third P-type doped region and a fourth P-type doped region respectively formed in the first p-well and the second p-well; a first n-type doped region formed in the first p-well and between the third and first p-type doped regions; and a second n-type doped region formed in the second p-well and between the second and fourth P-type region; wherein the first p-type doped region is connected to a first voltage supply of a first power domain, the third p-type doped region and the first n-type doped region are connected to a second voltage supply of the first power domain; wherein the second p-type doped region is connected to a third voltage supply of a second power domain, the fourth p-type doped region and the second n-type doped region are connected to a fourth voltage supply of the second power domain; and wherein the first and second power domains are different domains. ### Claim 2 (depends on 1) The cross-domain ESD protection device as claimed in claim 1, further comprising: a third n-type doped region formed in a first boundary region of the first p-well and the first n-well, and between the first n-type doped region and the first p-type doped region; a first gate structure formed on the first p-well and between the first n-type doped region and the third n-type doped region; a fourth n-type doped region formed in a second boundary region of the second p-well and the first n-well, and between the second n-type doped region and the second p-type doped region; and a second gate structure formed on the second p-well and between the second n-type doped region and the fourth n-type doped region; wherein the first and second gate structures are respectively connected to the second voltage supply and the fourth voltage supply. ### Claim 3 (depends on 1) The cross-domain ESD protection device as claimed in claim 1, further comprising: a p-type bias region formed in the first n-well and between the first p-type doped region and the second p-type doped region; a fifth p-type doped region and a seventh p-type doped region respectively formed in the first p-well and the first n-well, and disposed between the first n-type doped region and the first p-type doped region; a sixth p-type doped region and an eighth p-type doped region respectively formed in the second p-well and the first n-well, and disposed between the second n-type doped region and the second p-type doped region; a third gate structure formed on the first n-well and between the first and seventh p-type doped regions; a fourth gate structure formed on the first n-well and between the second and eighth p-type doped regions; wherein the fifth and seventh p-type doped regions are electrically connected and the sixth and eighth p-type doped regions are electrically connected, the third and fourth gate structures are connected to a detection node and the p-type bias region is connected to a bias voltage. ### Claim 4 (depends on 3) The cross-domain ESD protection device as claimed in claim 3, further comprising a bias circuit providing the bias voltage based on the first voltage supply and the third voltage supply, to reduce leakage current of the cross-domain ESD protection device. ### Claim 5 (depends on 4) The cross-domain ESD protection device as claimed in claim 4, wherein the bias circuit comprises a first PMOS transistor and a second PMOS transistor, connected in series, and the serially connected first and second PMOS transistors are further connected between the first voltage supply and the third voltage supply; wherein gates of the first and second PMOS transistors respectively connected to the third voltage supply and the first voltage supply, and bulks and a connection node of the first and second PMOS transistors are connected to the p-type bias region. ### Claim 6 (depends on 3) The cross-domain ESD protection device as claimed in claim 3, further comprising an ESD detection and trigger circuit, connected to the first, second, third and fourth p-type doped region, the p-type bias region, and the third and fourth gate structures; wherein the ESD detection and trigger circuit generates a detection voltage to the third and fourth gate structures to activate the cross-domain ESD protection device when an ESD event occurs at any of the first, second, third and fourth voltage supply. ### Claim 7 (depends on 6) The cross-domain ESD protection device as claimed in claim 6, wherein the ESD detection and trigger circuit comprises: a first diode having an anode and a cathode respectively connected to the third p-type doped region and the fourth p-type doped region; a second diode having a cathode and an anode respectively connected to the third p-type doped region and the fourth p-type doped region; a third diode and a fourth diode having anodes connected together and cathodes respectively connected to the third p-type doped region and the fourth p-type doped region; a capacitor connected between the anodes of the third and fourth diodes and the detection node; and a resistor connected between the detection node and the p-type bias region. ### Claim 8 (depends on 4) The cross-domain ESD protection device as claimed in claim 4, further comprising an ESD detection and trigger circuit, connected to the first, second, third and fourth p-type doped region, the p-type bias region, and the third and fourth gate structures; wherein the ESD detection and trigger circuit generates a detection voltage to the third and fourth gate structures to activate the cross-domain ESD protection device when an ESD event occurs at any of the first, second, third and fourth voltage supply. ### Claim 9 (depends on 8) The cross-domain ESD protection device as claimed in claim 8, wherein the ESD detection and trigger circuit comprises: a first diode having an anode and a cathode respectively connected to the third p-type doped region and the fourth p-type doped region; a second diode having a cathode and an anode respectively connected to the third p-type doped region and the fourth p-type doped region; a third diode and a fourth diode having anodes connected together and cathodes respectively connected to the third p-type doped region and the fourth p-type doped region; a capacitor connected between the anodes of the third and fourth diodes and the detection node; and a resistor connected between the detection node and the p-type bias region. ### Claim 10 (depends on 1) The cross-domain ESD protection device as claimed in claim 1, further comprising a fifth n-type doped region and a sixth n-type doped region respectively formed in the first p-well and the second p-well and respectively connected to the fourth voltage supply and the second voltage supply. ### Claim 11 (depends on 2) The cross-domain ESD protection device as claimed in claim 2, further comprising a fifth n-type doped region and a sixth n-type doped region respectively formed in the first p-well and the second p-well and respectively connected to the fourth voltage supply and the second voltage supply. ### Claim 12 (depends on 3) The cross-domain ESD protection device as claimed in claim 3, further comprising a fifth n-type doped region and a sixth n-type doped region respectively formed in the first p-well and the second p-well and respectively connected to the fourth voltage supply and the second voltage supply. ### Claim 13 A cross-domain electrostatic discharge protection device, comprising: a deep n-well formed in a substrate; a first p-well and a second p-well formed in the deep n-well; a first n-well formed in the deep n-well and between the first p-well and the second p-well, the first n-well contacting the first p-well and the second p-well; a first p-type doped region and a second p-type doped region formed in the first n-well; a third P-type doped region and a fourth P-type doped region respectively formed in the first p-well and the second p-well; a first n-type doped region formed in the first p-well and between the third and first p-type doped regions; and a second n-type doped region formed in the second p-well and between the second and fourth P-type region; a p-type bias region formed in the first n-well and between the first p-type doped region and the second p-type doped region; a fifth p-type doped region and a seventh p-type doped region respectively formed in the first p-well and the first n-well, and disposed between the first n-type doped region and the first p-type doped region; a sixth p-type doped region and an eighth p-type doped region respectively formed in the second p-well and the first n-well, and disposed between the second n-type doped region and the second p-type doped region; a third gate structure formed on the first n-well and between the first and seventh p-type doped regions; a fourth gate structure formed on the first n-well and between the second and eighth p-type doped regions; and an ESD detection and trigger circuit connected to the first, second, third and fourth p-type doped region, the p-type bias region, and the third and fourth gate structures; wherein the first p-type doped region is connected to a first voltage supply of a first power domain, the third p-type doped region and the first n-type doped region are connected to a second voltage supply of the first power domain; wherein the second p-type doped region is connected to a third voltage supply of a second power domain, the fourth p-type doped region and the second n-type doped region are connected to a fourth voltage supply of the second power domain; and wherein the first and second power domains are different domains; wherein the fifth and seventh p-type doped regions are electrically connected and the sixth and eighth p-type doped regions are electrically connected, the third and fourth gate structures are connected to a detection node and the p-type bias region is connected to a bias voltage; wherein the ESD detection and trigger circuit generates a detection voltage to the third and fourth gate structures to activate the cross-domain ESD protection device when an ESD event occurs at any of the first, second, third and fourth voltage supply. ### Claim 14 (depends on 13) The cross-domain ESD protection device as claimed in claim 13, wherein the ESD detection and trigger circuit comprises: a first diode having an anode and a cathode respectively connected to the third p-type doped region and the fourth p-type doped region; a second diode having a cathode and an anode respectively connected to the third p-type doped region and the fourth p-type doped region; a third diode and a fourth diode having anodes connected together and cathodes respectively connected to the third p-type doped region and the fourth p-type doped region; a capacitor connected between the anodes of the third and fourth diodes and the detection node; and a resistor connected between the detection node and the p-type bias region. ### Claim 15 (depends on 14) The cross-domain ESD protection device as claimed in claim 14, further comprising a bias circuit providing the bias voltage based on the first voltage supply and the third voltage supply, to reduce leakage current of the cross-domain ESD protection device. ### Claim 16 (depends on 15) The cross-domain ESD protection device as claimed in claim 15, wherein the bias circuit comprises a first PMOS transistor and a second PMOS transistor, connected in series, and the serially connected first and second PMOS transistors are further connected between the first voltage supply and the third voltage supply; wherein gates of the first and second PMOS transistors respectively connected to the third voltage supply and the first voltage supply, and bulks and a connection node of the first and second PMOS transistors are connected to the p-type bias region.