# US 9,437,586 B2 · Semiconductor package and method of fabricating the same

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- Number: US 9,437,586 B2
- Document ID: US9437586B2
- Status: Granted
- Kind: B2
- Application number: 14/503,575
- Filed: 2014-10-01
- Published: 2015-04-23
- Granted: 2016-09-06
- Earliest claimed: 2013-10-22
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Min Gi Hong
- Inventors: Min Gi Hong
- Web page: https://patentgrep.com/patent/US9437586B2

## CPC

- H10W 90/00: Package configurations
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 70/68: Shapes or dispositions thereof
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/655: Fan-out layouts
- H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage}
- H10W 70/682: {comprising holes having chips therein}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/075: {of bond wires}
- H10W 72/07553: {changes in shapes}
- H10W 72/07554: {changes in dispositions}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/537: {Multiple bond wires having different shapes}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/547: {Dispositions of multiple bond wires}
- H10W 72/5473: {multiple bond wires connected to a common bond pad}
- H10W 72/552: {comprising metals or metalloids, e.g. silver}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/859: {Bump connectors and bond wires}
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9413: {on encapsulations}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Provided is a semiconductor package in which a cell array region and a peripheral circuit region are formed as different semiconductor chips, respectively. First semiconductor chips including memory cells and a second semiconductor chip including only peripheral circuitry common to the first semiconductor chips are electrically connected to each other. Thus, a loading capacitance of the semiconductor package may be reduced. As a result, an RC delay of the semiconductor package may be reduced, thereby improving an operating speed of the semiconductor package.

## Claims

### Claim 1

A semiconductor package comprising:
a package substrate including a top surface, a bottom surface, and an opening;
a first semiconductor chip at a central region of the package substrate, the first semiconductor chip including peripheral circuits in a peripheral circuit region; and
a plurality of second semiconductor chips on a first region and a second region of the package substrate, the opening disposed between the first region and the second region of the package substrate, each of the plurality of second semiconductor chips including a cell array region in which memory cells are disposed,
wherein the peripheral circuits in the first semiconductor chip are configured to drive the memory cells in the second semiconductor chips,
wherein the first semiconductor chip partially overlaps with the opening and does not entirely cover the opening.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the peripheral circuit region further includes at least one of a conjunction region and a bitline sense amplifier region.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein
the first semiconductor chip and the second semiconductor chips are electrically connected to each other by wires disposed through the opening.

### Claim 4 (depends on 3)

The semiconductor package of claim 3, further comprising:
a mold layer covering the first semiconductor chip and the second semiconductor chips and filling the opening.

### Claim 5 (depends on 3)

The semiconductor package of claim 3, wherein
a portion of the opening is exposed by the first semiconductor chip, and
a distance between one side surface of the first semiconductor chip and one side surface of the opening is about 500 μmor more.

### Claim 6 (depends on 3)

The semiconductor package of claim 3, wherein
the package substrate includes a substrate conductive pattern on a top surface of the package substrate and adjacent to the opening,
the second semiconductor chips include wiring conductive patterns at their respective end portions, and
some of the wiring conductive patterns are connected to the substrate conductive pattern by a wire.

### Claim 7 (depends on 6)

The semiconductor package of claim 6, wherein a ground/power supply voltage is applied to the substrate conductive pattern.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, wherein
the second semiconductor chips are identical to each other,
the first semiconductor chip includes a first side and a second side being opposite to the first side, and
a first group of the second semiconductor chips at the first side of the first semiconductor chip and a second group of the second semiconductor chips at the second side of the first semiconductor chip are symmetrically disposed to each other about a vertical axis running through a center of the package substrate.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, wherein
the second semiconductor chips are identical to each other, and
a number of the second semiconductor chips at a first side of the first semiconductor chip is different from a number of the second semiconductor chips at a second side of the first semiconductor chip, the second side of the first semiconductor chip being opposite to the first side of the semiconductor chip.

### Claim 10

A semiconductor package comprising:
a package substrate;
a plurality of first semiconductor chips each including memory cells; and
a second semiconductor chip including peripheral circuitry common to the first semiconductor chips, the peripheral circuitry configured to drive together the memory cells in two or more of the first semiconductor chips, wherein
each of the first semiconductor chips does not include a peripheral circuitry configured to drive the memory cell and the second semiconductor chip does not include a memory cell,
the package substrate includes a top surface, a bottom surface, and an opening defined at a location,
the first semiconductor chips are on the top surface,
the second semiconductor chip is on the bottom surface and overlaps with the opening, and
the second semiconductor chip does not entirely cover the opening.

### Claim 11

A semiconductor package comprising:
a package substrate including a bottom surface, a top surface, and a hole;
a peripheral circuit chip at a central region of the bottom surface of the package substrate, wherein the peripheral circuit chip overlaps the hole; and
a plurality of memory chips including first to Nth memory chips on the top surface of the package substrate at both sides of the peripheral circuit chip,
wherein a second memory chip is stacked on the first memory chip by partially overlapping the first memory chip,
wherein the Nth memory chip is stacked on a N-1th memory chip by partially overlapping the N-1th memory chip,
wherein the Nth memory chip does not overlap with the hole, and
where “N” denotes a natural number of 2 or more.