# US 9,437,583 B1 · Package-on-package assembly and method for manufacturing the same

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- Number: US 9,437,583 B1
- Document ID: US9437583B1
- Status: Granted
- Kind: B1
- Application number: 15/134,396
- Filed: 2016-04-21
- Granted: 2016-09-06
- Earliest claimed: 2015-06-09
- Assignees: Inotera Memories, Inc.
- Applicants: Inotera Memories, Inc.
- Inventors: Shing-Yih Shih; Neng-Tai Shih
- Web page: https://patentgrep.com/patent/US9437583B1

## CPC

- H10W 90/00: Package configurations
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A package-on-package (PoP) assembly includes a bottom die package and a top die package. The bottom die package includes an interposer having a first side and a second side, an active chip mounted on the first side within a chip mounting area through first bumps, and a dummy chip mounted on the first side within a peripheral area. The dummy chip is directly mounted on a passivation layer of the interposer. A dielectric layer covers the active chip and the dummy chip. At least one TSV connecter penetrates through the dielectric layer and the dummy chip. A molding compound is disposed on the first side. The molding compound covers the active chip and the TSV chip. Solder bumps are mounted on the second side.

## Claims

### Claim 1

A package-on-package (PoP) assembly, comprising:
a bottom die package comprising
an interposer having a first side and a second side opposite to the first side;
at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps;
at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, wherein the dummy chip is directly mounted on a passivation layer of the interposer;
a dielectric layer covering the at least one active chip and the at least one dummy chip;
at least one TSV connecter penetrating through the dielectric layer and the dummy chip;
a molding compound disposed on the first side, the molding compound covering the at least one active chip and the at least one TSV chip; and
a plurality of solder bumps mounted on the second side;
a top die package mounted on the bottom die package.

### Claim 2 (depends on 1)

The PoP assembly according to claim 1, wherein the dummy chip is directly mounted on the passivation layer by using an adhesive.

### Claim 3 (depends on 1)

The PoP assembly according to claim 1, wherein TSV connecter is electrically connected to a metal trace pattern on the dielectric layer.

### Claim 4 (depends on 3)

The PoP assembly according to claim 3, wherein the top die package is mounted on the bottom die package through a plurality of second bumps disposed on the metal trace pattern.