# US 9,437,578 B2 · Stacked IC control through the use of homogenous region

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- Number: US 9,437,578 B2
- Document ID: US9437578B2
- Status: Granted
- Kind: B2
- Application number: 14/316,125
- Filed: 2014-06-26
- Published: 2015-12-31
- Granted: 2016-09-06
- Earliest claimed: 2014-06-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Wen-I Hsu; Cheng-Ying Ho; Jeng-Shyan Lin; Feng-Chi Hung; Dun-Nian Yaung
- Web page: https://patentgrep.com/patent/US9437578B2

## CPC

- H10W 90/00: Package configurations
- H10F 39/018: {of hybrid image sensors}
- H10F 39/026: {Wafer-level processing}
- H10F 39/809: {of hybrid image sensors}
- H10F 39/811: {Interconnections}
- H10P 50/642: {Chemical etching}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0238: {comprising etching via holes through pads or through electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/0253: {comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates}
- H10W 20/0265: {characterised by the sidewall insulation}
- H10W 20/071: {of dielectric parts thereof}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2125: {Top-view shapes}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 72/019: {of bond pads}
- H10W 72/90: Bond pads, in general
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/792: {between multiple chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A package includes a semiconductor chip. The semiconductor chip includes a substrate, a plurality of dielectric layers underlying the substrate, a dielectric region penetrating through the plurality of dielectric layers, and a metal pad overlapped by the dielectric region. A conductive plug penetrates through the substrate, the dielectric region, and the metal pad.

## Claims

### Claim 1

A package comprising:
a first semiconductor chip including:
a first substrate;
a first plurality of dielectric layers underlying the first substrate;
a dielectric region penetrating through the first plurality of dielectric layers; and
a first metal pad overlapped by the dielectric region; and
a conductive plug penetrating through the first substrate, the dielectric region, and the first metal pad, wherein an entirety of the dielectric region is underlying the first substrate.

### Claim 2 (depends on 1)

The package of claim 1, wherein the dielectric region penetrates through all Inter-Metal Dielectric (IMD) layers of the first semiconductor chip, and wherein the all IMD layers comprise the first plurality of dielectric layers.

### Claim 3 (depends on 1)

The package of claim 1, wherein the dielectric region forms a ring encircling the conductive plug.

### Claim 4 (depends on 1)

The package of claim 1, wherein the dielectric region is formed of a homogenous dielectric material.

### Claim 5 (depends on 1)

The package of claim 1 further comprising:
a second semiconductor chip underlying the first semiconductor chip, the second semiconductor chip comprising:
a second substrate;
a second plurality of dielectric layers over the second substrate, wherein one of the first plurality of dielectric layers is bonded to one of the second plurality of dielectric layers; and
a second metal pad in one of the second plurality of dielectric layers, wherein the conductive plug extends into the second semiconductor chip to contact a top surface of the second metal pad.

### Claim 6 (depends on 1)

The package of claim 1, wherein conductive plug comprises:
a first portion on a first side of the first metal pad, wherein the first portion has a first width; and
a second portion with a portion in the first metal pad and an additional portion on a second side of the first metal pad, wherein the second portion has a second width smaller than the first width.

### Claim 7 (depends on 1)

The package of claim 1, wherein the dielectric region comprises a first surface and a second surface opposite to the first surface, with the first surface and the second surface being opposite surfaces parallel to a major surface of the first substrate, and the first surface and the second surface are both underlying the first substrate.

### Claim 8

A package comprising:
a first semiconductor chip comprising:
a first substrate;
a first plurality of dielectric layers; and
a homogenous dielectric region in the first plurality of dielectric layers;
a second semiconductor chip comprising:
a second substrate;
a second plurality of dielectric layers over the second substrate, wherein the first plurality of dielectric layers is bonded to the second plurality of dielectric layers; and
a metal pad in one of the second plurality of dielectric layers; and
a conductive plug penetrating through the first substrate and the homogenous dielectric region, and extends to the metal pad.

### Claim 9 (depends on 8)

The package of claim 8 further comprising an additional metal pad in the first semiconductor chip, wherein the conductive plug penetrates through the additional metal pad, and stops on a top surface of the metal pad.

### Claim 10 (depends on 9)

The package of claim 9, wherein the additional metal pad is located between the homogenous dielectric region and the metal pad in the second semiconductor chip.

### Claim 11 (depends on 9)

The package of claim 9, wherein the additional metal pad fully encircles the conductive plug.

### Claim 12 (depends on 8)

The package of claim 8, wherein the homogenous dielectric region fully encircles the conductive plug.

### Claim 13 (depends on 8)

The package of claim 8, wherein one of the first plurality of dielectric layers is in physical contact with, and physically bonded to, one of the second plurality of dielectric layers.

### Claim 14

A method comprising:
forming a dielectric region penetrating through a plurality of dielectric layers in a first wafer;
forming a first metal pad aligned to the dielectric region, with the first metal pad comprising a first opening;
bonding the first wafer to a second wafer;
etching the first wafer that has the first opening in the first metal pad to form a second opening penetrating through the first wafer and extending into the second wafer, wherein the second opening penetrates through the dielectric region and the first opening in the first metal pad, and wherein a second metal pad in the second wafer is exposed through the second opening; and
filling the second opening with a conductive material to form a conductive plug.

### Claim 15 (depends on 14)

The method of claim 14, wherein the forming the dielectric region comprises:
etching the plurality of dielectric layers to form a third opening; and
filling the third opening with a homogenous dielectric material.

### Claim 16 (depends on 15)

The method of claim 15, wherein after the etching the plurality of dielectric layers, an Inter-Layer Dielectric (ILD) is exposed to the third opening.

### Claim 17 (depends on 16)

The method of claim 16, wherein after the etching the plurality of dielectric layers, a dielectric layer contacting an Inter-Layer Dielectric (ILD) is exposed to the third opening.

### Claim 18 (depends on 14)

The method of claim 14, wherein in the etching the first wafer, the first metal pad acts as an etching mask during the etching for forming a lower portion of the second opening.

### Claim 19 (depends on 14)

The method of claim 14 further comprising, after the bonding and before the etching the first wafer to form the second opening, thinning a semiconductor substrate of the first wafer.

### Claim 20 (depends on 14)

The method of claim 14, wherein the forming the dielectric region is performed after all low-k dielectric layers in the first wafer are formed.