# US 9,437,576 B1 · Semiconductor device package and method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,576 B1 - Document ID: US9437576B1 - Status: Granted - Kind: B1 - Application number: 14/665,800 - Filed: 2015-03-23 - Published: 2016-09-29 - Granted: 2016-09-06 - Earliest claimed: 2015-03-23 - Assignees: Advanced Semiconductor Engineering, Inc. - Applicants: Advanced Semiconductor Engineering, Inc. - Inventors: Tau-Jing Yang; Kuo-Feng Huang; Wei Yu Nien - Web page: https://patentgrep.com/patent/US9437576B1 ## CPC - H10W 90/00: Package configurations - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 42/276: {the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation} - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 74/131: {the semiconductor body being only partially enclosed} - H10W 46/106: {digital information, e.g. bar codes} - H10W 46/401: {for identification or tracking} - H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device package includes a substrate, a first electrical component, a second electrical component, and a conductive frame disposed on a top surface of the substrate. The conductive frame has a top portion and a rim substantially perpendicular to the top portion. The conductive frame covers the first electrical component, and includes at least one opening in the top portion of the conductive frame, one of which openings exposes the second electrical component. A top surface of the top portion of the conductive frame is substantially coplanar with a top surface of the second electrical component. The semiconductor device package further includes an electromagnetic interference shield in contact with the top surface of the top portion of the conductive frame, an outer lateral surface of the rim of the conductive frame, and the top surface of the second electrical component. ## Claims ### Claim 1 A semiconductor device package, comprising a substrate having a top surface; a first electrical component disposed on the top surface of the substrate; a second electrical component disposed on the top surface of the substrate, the second electrical component having a top surface; a conductive frame defining a top portion and a rim substantially perpendicular to the top portion, the top portion having a top surface, the conductive frame disposed on the top surface of the substrate to cover the first electrical component, the conductive frame including at least one opening in the top portion of the conductive frame, the at least one opening exposing the second electrical component, and the top surface of the top portion of the conductive frame being substantially coplanar with the top surface of the second electrical component; and an electromagnetic interference shield in contact with the top surface of the top portion of the conductive frame, an outer lateral surface of the rim of the conductive frame, and the top surface of the second electrical component. ### Claim 2 (depends on 1) The semiconductor device package of claim 1, wherein the first electrical component includes a plurality of electrical contacts, further comprising an underfill to encapsulate the plurality of electrical contacts. ### Claim 3 (depends on 1) The semiconductor device package of claim 1, wherein the conductive frame is disposed on the top surface of the substrate through a connection member. ### Claim 4 (depends on 3) The semiconductor device package of claim 3, wherein the connection member is separated from the first electrical component by a distance equal to or smaller than 0.2 millimeter. ### Claim 5 (depends on 1) The semiconductor device package of claim 1, further comprising a pattern formed in the top portion of the conductive frame. ### Claim 6 (depends on 1) The semiconductor device package of claim 1, further comprising a pattern formed in the electromagnetic interference shield. ### Claim 7 (depends on 1) The semiconductor device package of claim 1, further comprising at least one insulation pad formed on a bottom surface of the electromagnetic interference shield, wherein each of the at least one insulation pad contacts the top surface of the second electrical component. ### Claim 8 (depends on 1) The semiconductor device package of claim 1, further comprising a third electrical component disposed on the top surface of the substrate, wherein the conductive frame includes at least one compartment extending from the top portion of the conductive frame to separate the first electrical component from the third electrical component. ### Claim 9 (depends on 1) The semiconductor device package of claim 1, wherein the second electrical component extends vertically the highest in the semiconductor package. ### Claim 10 A method of manufacturing a semiconductor device package, comprising (a) providing a substrate having a top surface; (b) attaching a first electrical component and a second electrical component on the top surface of the substrate; (c) placing a conductive frame on the top surface of the substrate to cover the first electrical component, the conductive frame including a top portion and a rim substantially perpendicular to the top portion, the top portion having a top surface, the conductive frame defining at least one opening in the top portion of the conductive frame, the least one opening exposing the second electrical component, and the top surface of the top portion of the conductive frame being substantially coplanar with a top surface of the second electrical component; and (d) placing an electromagnetic interference shield on the conductive frame in contact with the top surface of the top portion of the conductive frame, an outer lateral surface of the rim of the conductive frame, and the top surface of the second electrical component. ### Claim 11 (depends on 10) The method of claim 10, further comprising forming an underfill to encapsulate a plurality of electrical contacts of the first electrical component. ### Claim 12 (depends on 11) The method of claim 11, wherein the underfill is formed by injecting or dispensing an electrically insulating material through the opening of the conductive frame above the first electrical component. ### Claim 13 (depends on 11) The method of claim 11, wherein the underfill is formed subsequent to placing the conductive frame in (c). ### Claim 14 (depends on 10) The method of claim 10, wherein the first electrical component, the second electrical component and the conductive frame are secured on the top surface of the substrate by a reflow process. ### Claim 15 (depends on 10) The method of claim 10, further comprising forming a pattern in the top portion of the conductive frame. ### Claim 16 (depends on 15) The method of claim 15, wherein prior to placing the EMI shield in (d), the pattern is scanned to read information corresponding to the semiconductor device package. ### Claim 17 (depends on 10) The method of claim 10, wherein in placing the conductive frame in (c), the conductive frame is placed on a connection member located on the top surface of the substrate. ### Claim 18 (depends on 10) The method of claim 10, further comprising forming at least one insulation pad on a bottom surface of the electromagnetic interference shield, positioned so as to be in contact with the top surface of the second electrical component. ### Claim 19 (depends on 10) The method of claim 10, further comprising forming at least one compartment extending from the top portion of the conductive frame to separate the first electrical component from a third electrical component disposed on the top surface of the substrate. ### Claim 20 (depends on 10) The method of claim 10, further comprising forming a pattern in the electromagnetic interference shield.