# US 9,437,575 B1 · Semiconductor device package formed in a chip-on-wafer last process using thin film adhesives

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- Number: US 9,437,575 B1
- Document ID: US9437575B1
- Status: Granted
- Kind: B1
- Application number: 14/159,237
- Filed: 2014-01-20
- Granted: 2016-09-06
- Earliest claimed: 2014-01-20
- Assignees: Amkor Technology, Inc.
- Applicants: Amkor Technology, Inc.
- Inventors: Michael G. Kelly; David Jon Hiner; Ji Hun Lee; Won Chul Do; Doo Hyun Park; Ronald Huemoeller
- Web page: https://patentgrep.com/patent/US9437575B1

## CPC

- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/0198: {batch processes}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/016: {using moulds}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 76/12: characterised by their shape
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7418: {of passive members, e.g. a chip mounting substrate}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/685: comprising multiple insulating layers
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods for a semiconductor device package formed in a chip-on-wafer last process using thin film adhesives are disclosed and may include bonding a first carrier to a first surface of an interposer in wafer form, forming conductive bumps on a second surface of the interposer, bonding a second carrier to the conductive bumps utilizing a film adhesive, removing the first carrier from the interposer, bonding a semiconductor die to the first surface of the interposer, and encapsulating the die and the first surface of the interposer in an encapsulant material. The second carrier and the film adhesive may be removed from the conductive bumps utilizing a slide-off process. The interposer and encapsulant may be diced into a plurality of interposer and die structures. One of the die and interposer structures may be bonded to a substrate. The die may be bonded to the interposer utilizing a mass reflow process.

## Claims

### Claim 1

A method for semiconductor packaging, the method comprising:
forming front-side pads on a first surface of an interposer in wafer form;
bonding a first carrier directly to the first surface of the interposer;
exposing through-silicon vias (TSVs) in a second surface of the interposer;
forming conductive bumps on the exposed TSVs;
bonding a second carrier to the conductive bumps utilizing a film adhesive;
removing the first carrier from the interposer;
bonding one or more semiconductor die to the front-side pads on the first surface of the interposer;
removing the second carrier and the film adhesive from the conductive bumps;
dicing the interposer into a plurality of interposer and die structures; and
bonding one of the plurality of die and interposer structures to a substrate.

### Claim 2 (depends on 1)

The method according to claim 1, comprising bonding the one or more semiconductor die to the interposer utilizing a mass reflow process.

### Claim 3 (depends on 2)

The method according to claim 2, comprising utilizing a capillary underfill material after bonding the one or more semiconductor die to the interposer.

### Claim 4 (depends on 1)

The method according to claim 1, comprising bonding the one of the plurality of interposer and die structures to the substrate utilizing the conductive bumps formed on the exposed TSVs.

### Claim 5 (depends on 4)

The method according to claim 4, comprising bonding the one of the plurality of interposer and die structures to the substrate utilizing a mass reflow process on the conductive bumps formed on the exposed TSVs.

### Claim 6 (depends on 1)

The method according to claim 1, comprising encapsulating the one or more semiconductor die and at least a portion of the first surface of the interposer utilizing an encapsulant.

### Claim 7 (depends on 6)

The method according to claim 6, comprising grinding the encapsulant to expose a surface of the one or more semiconductor die.

### Claim 8 (depends on 1)

The method according to claim 1, comprising removing the second carrier and the film adhesive from the conductive bumps utilizing a slide-off process.

### Claim 9 (depends on 1)

The method according to claim 1, wherein an under bump metal is on the second surface of the interposer.

### Claim 10 (depends on 9)

The method according to claim 9, wherein conductive bumps are on the under bump metal on the second surface of the interposer.

### Claim 11 (depends on 10)

The method according to claim 10, comprising bonding the one of the plurality of interposer and die structures to the substrate utilizing the conductive bumps on the under bump metal on the second surface of the interposer.

### Claim 12 (depends on 11)

The method according to claim 11, comprising bonding the one of the plurality of interposer and die structures to the substrate utilizing a mass reflow process on the conductive bumps on the under bump metal on the second surface of the interposer.

### Claim 13 (depends on 1)

The method according to claim 1, comprising bonding the one of the plurality of interposer and die structures to the substrate utilizing conductive bumps on the substrate.

### Claim 14 (depends on 1)

The method according to claim 1, wherein the conductive bumps on the exposed TSVs comprise copper.

### Claim 15

A method for semiconductor packaging, the method comprising:
providing an interposer in wafer form with front-side pads on a first surface of the interposer;
bonding a first carrier directly to the first surface of the interposer;
exposing vias in a second surface of the interposer;
forming contacts on the exposed vias;
bonding a second carrier to the contacts utilizing an adhesive;
removing the first carrier from the interposer;
bonding one or more semiconductor die to the front-side pads on the first surface of the interposer;
removing the second carrier and the adhesive from the contacts;
dicing the interposer into a plurality of interposer and die structures; and
bonding one of the plurality of die and interposer structures to a substrate.

### Claim 16 (depends on 15)

The method according to claim 15, comprising bonding one of the plurality of interposer and die structures to a substrate utilizing the conductive bumps formed on the exposed vias.

### Claim 17 (depends on 15)

The method according to claim 15, wherein the contacts on the exposed vias comprise conductive bumps.

### Claim 18 (depends on 15)

The method according to claim 15, comprising encapsulating the one or more semiconductor die and at least a portion of the first surface of the interposer utilizing an encapsulant.

### Claim 19 (depends on 18)

The method according to claim 18, comprising grinding the encapsulant to expose a surface of the one or more semiconductor die.