# US 9,437,569 B2 · High density substrate routing in BBUL package

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,437,569 B2
- Document ID: US9437569B2
- Status: Granted
- Kind: B2
- Application number: 14/922,425
- Filed: 2015-10-26
- Published: 2016-03-17
- Granted: 2016-09-06
- Earliest claimed: 2012-12-06
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Weng Hong Teh; Chia-Pin Chiu
- Web page: https://patentgrep.com/patent/US9437569B2

## CPC

- H10W 90/00: Package configurations
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 72/00: Interconnections or connectors in packages
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/654: Top-view layouts
- H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/853: {On the same surface}
- H10W 72/9413: {on encapsulations}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

## Claims

### Claim 1

A device including:
a substrate including a conductive bus on or at least partially therein;
a first die at least partially embedded in the substrate, the first die including a first plurality of high density interconnect pads and a first plurality of low density interconnect pads, the first plurality of low density interconnect pads electrically coupled to the bus;
a second die at least partially embedded in the substrate, the second die including a second plurality of high density interconnect pads and a second plurality of low density interconnect pads, the second plurality of low density interconnect pads electrically coupled to the bus; and
a high density interconnect element embedded in the substrate, the high density interconnect element including a third plurality of high density interconnect pads each electrically coupled to an interconnect pad of each of the first and second plurality of high density interconnect pads, wherein the high density interconnect element is selected from a group including a silicon die interconnect bridge and a glass die interconnect bridge.

### Claim 2 (depends on 1)

The device of claim 1, further comprising encapsulant on the high density interconnect element.

### Claim 3 (depends on 1)

The device of claim 1, further comprising at least one buildup layer formed over the high density interconnect element.

### Claim 4 (depends on 1)

The device of claim 1, wherein the first die is a logic die and the second die is an analog die.

### Claim 5 (depends on 1)

The device of claim 1, wherein the substrate is a Bumpless Buildup Layer (BBUL) substrate.

### Claim 6 (depends on 1)

The device of claim 1, further comprising a first die backside film on a non-active surface of the first die.

### Claim 7 (depends on 6)

The of device of claim 6, further comprising a second die backside film on a non-active surface of the second die.

### Claim 8 (depends on 1)

The device of claim 1, wherein the bus is a power bus or a ground bus.

### Claim 9 (depends on 1)

The device of claim 1, wherein the first and second plurality of low density interconnect pads include up to about twenty-three pads per millimeter per layer.

### Claim 10 (depends on 1)

The device of claim 1, wherein the first, second, and third high density interconnect pads include greater than twenty-three pads per millimeter per layer and less than about two hundred fifty pads per millimeter per layer.

### Claim 11 (depends on 1)

The device of claim 1, wherein an interconnect pad of the first plurality of high density interconnect pads is electrically connected to a first interconnect pad of the third plurality of high density interconnect pads, an interconnect pad of the second plurality of high density interconnect pads is electrically connected to a second interconnect pad of the third plurality of high density interconnect pads, and the first interconnect pad of the third plurality of high density interconnect pads is electrically connected to the second interconnect pad of the third plurality of high density interconnect pads by a trace.

### Claim 12 (depends on 11)

The device of claim 11, wherein the interconnect pad of the first plurality of high density interconnect pads is electrically connected to a data line of the first die.

### Claim 13

A device comprising:
a substrate;
a first die at least partially embedded in a first layer of the substrate, the first die including a first plurality of high density interconnect pads and a first plurality of low density interconnect pads on a first side thereof;
a second die at least partially embedded in the first layer of the substrate, the second die including a second plurality of high density interconnect pads and a second plurality of low density interconnect pads on a first side thereof;
a high density interconnect element embedded in the substrate in a different layer than the first layer, the high density interconnect element including a third plurality of high density interconnect pads on a side facing the first and second dies, one or more interconnect pads of the third plurality of high density interconnect pads electrically coupled to an interconnect pad of the first and second plurality of high density interconnect pads; and
a plurality of vias in different layers of the substrate than the first layer, a via of the plurality of vias electrically connected to a respective interconnect pad of the first and second pluralities of low density interconnect pads.

### Claim 14 (depends on 13)

The device of claim 13, wherein the first die is a logic die and the second die is an analog die.

### Claim 15 (depends on 13)

The device of claim 13, wherein the high density interconnect element is one of a silicon die interconnect bridge and a glass die interconnect bridge.

### Claim 16 (depends on 13)

The device of claim 13, wherein the plurality of vias are electrically coupled to a power bus or a ground bus.

### Claim 17 (depends on 13)

The device of claim 13, wherein the first and second low density interconnect pads include up to about twenty-three pads per millimeter per layer.

### Claim 18 (depends on 13)

The device of claim 13, wherein the first, second, and third high density interconnect pads include between about twenty-three pads per millimeter per layer and two hundred fifty pads per millimeter per layer.

### Claim 19 (depends on 13)

The device of claim 13, further comprising a first die backside film on a second side of the first die opposite the first side.

### Claim 20 (depends on 13)

The device of claim 13, further comprising a second die backside film on a second side of the second die opposite the first side.