# US 9,437,568 B2 · Method for manufacturing semiconductor device having a multilayer interconnection > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,568 B2 - Document ID: US9437568B2 - Status: Granted - Kind: B2 - Application number: 14/518,389 - Filed: 2014-10-20 - Published: 2015-06-11 - Granted: 2016-09-06 - Earliest claimed: 2013-12-11 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Kabushiki Kaisha Toshiba - Inventors: Atsuko Kawasaki - Web page: https://patentgrep.com/patent/US9437568B2 ## CPC - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 90/00: Package configurations - H10P 50/73: {using masks for insulating materials} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/01: {Manufacture or treatment} - H10W 72/01931: {using blanket deposition} - H10W 72/01953: {by etching} - H10W 72/0198: {batch processes} - H10W 72/941: {Dispositions of bond pads} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure} - H10W 80/312: {characterised by the direct bonding of electrically conductive pads} - H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers} - H10W 80/333: {Compression bonding} - H10W 80/743: {having disposition changed during the connecting} - H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL - H10W 90/722: {between stacked chips} - H10W 90/792: {between multiple chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer, forming a second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer, forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than the surface of the first conductive layer, the partial area containing surroundings of the first conductive layer, and connecting the surface of the first conductive layer and the surface of the second conductive layer and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer. ## Claims ### Claim 1 A method for manufacturing a semiconductor device comprising: forming a first interconnection layer on a first substrate, the first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer; forming a second interconnection layer on a second substrate, the second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer; forming a first resist layer on a predetermined area of a surface of the first insulating layer exposed from the surface of the first interconnection layer; forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than a surface of the first conductive layer by etching the first insulating layer exposed from the first resist layer, the partial area containing surroundings of the first conductive layer; and electrically connecting the surface of the first conductive layer and a surface of the second conductive layer and also bonding the surface of the first insulating layer excluding the first non-bonded surface and a surface of the second insulating layer. ### Claim 2 (depends on 1) The method for manufacturing a semiconductor device according to claim 1, wherein the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer are bonded such that a space is formed between the first non-bonded surface and the second insulating layer. ### Claim 3 (depends on 2) The method for manufacturing a semiconductor device according to claim 2, wherein the space is formed by the first non-bonded surface and the second insulating layer being spaced and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer. ### Claim 4 (depends on 3) The method for manufacturing a semiconductor device according to claim 3, wherein a portion of a conductive material formed by the surface of the first conductive layer and the surface of the second conductive layer being bonded is arranged inside the space. ### Claim 5 (depends on 1) The method for manufacturing a semiconductor device according to claim 1, wherein the first substrate is a first wafer and the second substrate is a second wafer; and the first resist layer is formed on a dicing line on the surface of the first insulating layer. ### Claim 6 (depends on 1) The method for manufacturing a semiconductor device according to claim 1, wherein the first substrate is a first wafer and the second substrate is a second wafer; and the first resist layer is formed on a dicing line on the surface of the first insulating layer and along a circumference of the first wafer on the surface of the first insulating layer. ### Claim 7 (depends on 1) The method for manufacturing a semiconductor device according to claim 1, wherein a second non-bonded surface is formed on the surface of the second insulating layer by making the partial area containing the surroundings of the second conductive layer of the surface of the second insulating layer lower than the surface of the second conductive layer; and the surface of the first conductive layer and the surface of the second conductive layer are electrically connected and the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer excluding the second non-bonded surface are bonded. ### Claim 8 (depends on 7) The method for manufacturing a semiconductor device according to claim 7, wherein the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer excluding the second non-bonded surface are bonded such that a space is formed between the first non-bonded surface and the second non-bonded surface. ### Claim 9 (depends on 8) The method for manufacturing a semiconductor device according to claim 8, wherein the space is formed by the first non-bonded surface and the second non-bonded surface being spaced and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer excluding the second non-bonded surface. ### Claim 10 (depends on 9) The method for manufacturing a semiconductor device according to claim 9, wherein a portion of a conductive material formed by the surface of the first conductive layer and the surface of the second conductive layer being bonded is arranged inside the space. ### Claim 11 (depends on 7) The method for manufacturing a semiconductor device according to claim 7, wherein the first non-bonded surface is formed by forming a first resist layer on a predetermined area of the surface of the first insulating layer exposed from the surface of the first interconnection layer, and making the partial area of the surface of the first insulating layer lower than the surface of the first conductive layer by etching the first insulating layer exposed from the first resist layer, and the second non-bonded surface is formed by forming a second resist layer on a predetermined area of the surface of the second insulating layer exposed from the surface of the second interconnection layer, and making the partial area of the surface of the second insulating layer lower than the surface of the second conductive layer by etching the second insulating layer exposed from the second resist layer. ### Claim 12 (depends on 11) The method for manufacturing a semiconductor device according to claim 11, wherein the first substrate is a first wafer and the second substrate is a second wafer; the first resist layer is formed on a dicing line on the surface of the first insulating layer; and the second resist layer is formed on a dicing line on the surface of the second insulating layer. ### Claim 13 (depends on 11) The method for manufacturing a semiconductor device according to claim 11, wherein the first substrate is a first wafer and the second substrate is a second wafer; the first resist layer is formed on a dicing line on the surface of the first insulating layer and along a circumference of the first wafer on the surface of the first insulating layer; and the second resist layer is formed on a dicing line on the surface of the second insulating layer and along a circumference of the second wafer on the surface of the second insulating layer.