# US 9,437,567 B2 · Semiconductor devices with ball strength improvement

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- Number: US 9,437,567 B2
- Document ID: US9437567B2
- Status: Granted
- Kind: B2
- Application number: 14/515,346
- Filed: 2014-10-15
- Published: 2015-01-29
- Granted: 2016-09-06
- Earliest claimed: 2011-11-08
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Tsung-Yuan Yu; Hsien-Wei Chen; Ying-Ju Chen; Shih-Wei Liang
- Web page: https://patentgrep.com/patent/US9437567B2

## CPC

- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/90: Bond pads, in general
- G06F 2113/18: Chip packaging
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/66: Conductive materials thereof
- H10W 70/69: Insulating materials thereof
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/231: {Shapes}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/263: {Providing mechanical bonding or support, e.g. dummy bumps}
- H10W 72/267: {Multiple bump connectors having different functions}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A semiconductor device includes a contact region over a substrate. The semiconductor device further includes a metal pad over the contact region. Additionally, the semiconductor device includes a post passivation interconnect (PPI) line over the metal pad, where the PPI line is in contact with the metal pad. Furthermore, the semiconductor device includes an under-bump-metallurgy (UBM) layer over the PPI line. Moreover, the semiconductor device includes a plurality of solder balls over the UBM layer, the plurality of solder balls being arranged at some, but not all, intersections of a number of columns and rows of a ball pattern.

## Claims

### Claim 1

A semiconductor device, comprising:
a contact region over a substrate, wherein the contact region is electrically coupled to an integrated circuit in or on the substrate;
a metal pad over the contact region;
a post passivation interconnect (PPI) line over the metal pad, wherein the PPI line is in contact with the metal pad;
a dielectric material over the PPI line;
a bump pattern which includes a plurality of bumps arranged in a number of columns and rows over an upper surface of the dielectric material, wherein the plurality of bumps include a plurality of connection bumps and a plurality of dummy bumps;
wherein a connection bump of the bump pattern is electrically coupled to the integrated circuit through the PPI line, the metal pad, and the contact region; and
wherein a dummy bump of the bump pattern is electrically isolated from the integrated circuit and wherein the plurality of dummy bumps are arranged asymmetrically with regard to a central region of the bump pattern.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the columns and the rows are perpendicular to each other.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the bump pattern is free of any isolated bumps, wherein an isolated bump is a bump having at most one bump in an adjacent intersection of the columns and rows.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein an intersection of the columns and rows in a corner of the bump pattern is free of any bump of the plurality of bumps.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising:
a under-bump-metallurgy (UBM) layer made up of a plurality of UBM regions that are spaced apart from one another, wherein a first of the UBM regions is disposed between the connection bump and the PPI line and wherein a second of the UBM regions is disposed over an upper surface of the dielectric material under the dummy bump; and
wherein the connection bump and dummy bump are included as part of the plurality of bumps over the UBM layer, the plurality of bumps arranged at some, but not all, intersections of a number of columns and rows of the bump pattern.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, further comprising an adhesive layer between the PPI line and the UBM layer, wherein the adhesive layer comprises at least one of titanium, titanium nitride, tantalum, or tantalum nitride.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein, at least in corner regions of the bump pattern, every connection bump of the plurality of connection bumps and dummy bump of the plurality of dummy bumps has at least two directly neighboring bumps in neighboring rows or columns, the at least two neighboring bumps being connection bumps, dummy bumps, or a combination of connection bumps and dummy bumps.

### Claim 8

A semiconductor device, comprising:
a contact region over a substrate, wherein the contact region is electrically coupled to an integrated circuit in or on the substrate;
a metal pad over the contact region, wherein the metal pad is in contact with the contact region;
a post passivation interconnect (PPI) line over the metal pad;
a polymer layer over the PPI line, wherein the polymer layer includes an opening aligned over a portion of the PPI line;
an under-bump-metallurgy (UBM) layer which includes a first UBM region disposed in the opening over the portion of the PPI line and a second UBM region disposed on the polymer layer and spaced apart from the first UBM region;
a plurality of bumps over the UBM layer, the plurality of bumps being arranged at some, but not all, intersections of a number of columns and rows of a bump pattern wherein, at least in corner regions of the bump pattern, each bump among the plurality of bumps has at least two directly neighboring bumps in neighboring rows or columns;
a connection bump over the first UBM region, wherein the connection bump is electrically coupled to the contact region through the first UBM region, the PPI line, and the metal pad; and
a dummy bump over the second UBM region and electrically isolated from the integrated circuit.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein at least one bump of the at least two neighboring bumps is either in the same row or column of the each bump among the plurality of bumps.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the PPI line has a thickness less than 30 micrometers (μm).

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein the bump pattern is free of any isolated bumps, wherein an isolated bump is a bump having at most one bump in an adjacent intersections of the columns and rows.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein at least one intersection of the columns and rows in a corner of the bump pattern is free of any bump of the plurality of bumps.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, further comprising a seed layer between the PPI layer and the UBM layer, wherein the seed layer comprises at least one of aluminum, copper alloy, silver, or gold.

### Claim 14 (depends on 8)

The semiconductor device of claim 8 wherein, the polymer layer comprises epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or polyimide.

### Claim 15 (depends on 8)

The semiconductor device of claim 8, further comprising an adhesive layer between the PPI layer and the UBM layer, wherein the adhesive layer comprises at least one of titanium, titanium nitride, tantalum, or tantalum nitride.

### Claim 16 (depends on 8)

The semiconductor device of claim 8, wherein the columns and the rows are perpendicular to each other.

### Claim 17 (depends on 8)

The semiconductor device of claim 8, wherein a plurality of dummy bumps are arranged asymmetrically with regard to a central region of the bump pattern.

### Claim 18

A semiconductor device with improved bump strength, said semiconductor device comprising:
a chip having an active surface;
a plurality of connection bumps on the active surface and in electrical connection with the chip, said connection bumps being arranged at some, but not all, intersections of a number of columns and rows of a bump pattern; and
a plurality of dummy bumps on the active surface but not in electrical connection with the chip, said dummy bumps being arranged at intersections where the connection bumps are not arranged and leaving some intersections without connection bumps and without dummy bumps;
wherein, at least in corner regions of the chip, every connection bump of the plurality of connection bumps and dummy bump of the plurality of dummy bumps has at least two neighboring bumps in at least two directly neighboring intersections, respectively, the at least two neighboring bumps being connection bumps, dummy bumps, or a combination of connection bumps and dummy bumps.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein
at least one connection bump of the plurality of connection bumps outside in one of the corner regions of the chip has one or fewer neighboring connection bumps.

### Claim 20 (depends on 18)

The semiconductor device of claim 18, further comprising:
a substrate having opposite surfaces one of which is mechanically connected to said chip by said plurality of connection bumps and the plurality of dummy bumps, and electrically connected to said chip via said plurality of connection bumps;
an encapsulant on said one surface of the substrate and covering the chip and the plurality of connection bumps and the plurality of dummy bumps; and
bumps on the other surface of the substrate and in electrical connection with the corresponding connection bumps of the plurality of connection bumps via the substrate.