# US 9,437,565 B2 · Semiconductor substrate and semiconductor package structure having the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,565 B2 - Document ID: US9437565B2 - Status: Granted - Kind: B2 - Application number: 14/586,735 - Filed: 2014-12-30 - Published: 2016-06-30 - Granted: 2016-09-06 - Earliest claimed: 2014-12-30 - Assignees: Advanced Seminconductor Engineering, Inc. - Applicants: Advanced Semiconductor Engineering, Inc. - Inventors: Guo-Cheng Liao; Chia-Ching Chen; Yi-Chuan Ding - Web page: https://patentgrep.com/patent/US9437565B2 ## CPC - H05K 3/007: {Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier (H05K1/187, H05K3/20 and H05K3/4682 take precedence)} - H10W 70/095: {of vias therein} - H10W 70/635: {Through-vias} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H05K 3/205: {using a pattern electroplated or electroformed on a metallic carrier} - H05K 3/4682: {Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil} - H05K 2201/09509: Blind vias, i.e. vias having one side closed - H05K 2201/10378: Interposers - H05K 2201/10674: Flip chip - H10W 72/01235: {by plating, e.g. electroless plating or electroplating} - H10W 72/01236: {in solid form, e.g. by using a powder or by laminating a foil} - H10W 72/01253: {by etching} - H10W 72/072: {of bump connectors} - H10W 72/07227: {involving guiding structures, e.g. spacers or supporting members} - H10W 72/07236: {Soldering or alloying} - H10W 72/07252: {changes in structures or sizes} - H10W 72/07254: {changes in dispositions} - H10W 72/07255: {changes in materials} - H10W 72/073: {of die-attach connectors} - H10W 72/221: {Structures or relative sizes} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/245: {of outermost layers of multilayered bumps, e.g. bump coating being only on a part of a bump core} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/2528: {Intermetallic compounds} - H10W 72/255: {of outermost layers of multilayered bumps, e.g. material of a coating} - H10W 72/287: {Flow barriers} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL} - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The present disclosure relates to a semiconductor package structure including a semiconductor substrate, a semiconductor chip and a conductive material. The semiconductor substrate includes an insulating layer, a conductive circuit layer and a conductive bump. The conductive circuit layer is recessed from the top surface of the insulating layer, and includes at least one pad. The conductive bump is disposed on the at least one pad. A side surface of the conductive bump, a top surface of the at least one pad and a side surface of the insulating layer together define an accommodating space. The conductive material is electrically connected the conductive bump and the semiconductor chip, and a portion of the conductive material is disposed in the accommodating space. ## Claims ### Claim 1 A semiconductor package structure, comprising: a substrate comprising: an insulating layer having a top surface; a conductive circuit layer recessed from the top surface of the insulating layer, wherein the conductive circuit layer comprises at least one pad and a trace, and the trace is exposed from the insulating layer; and a conductive bump disposed on the at least one pad, wherein a side surface of the conductive bump, a top surface of the at least one pad and a side surface of the insulating layer together define an accommodating space; a semiconductor chip; and a conductive material electrically connecting the conductive bump and the semiconductor chip; wherein a portion of the conductive material is disposed in the accommodating space; and wherein the conductive bump comprises a main portion, a metal layer portion and a protrusion portion, the protrusion portion protrudes from the at least one pad, the metal layer portion is disposed on the protrusion portion, the main portion is disposed on the metal layer portion, and widths of the main portion, the metal layer portion and the protrusion portion are substantially the same. ### Claim 2 (depends on 1) The semiconductor package structure according to claim 1, wherein a ratio of a width of the conductive bump to a width of the at least one pad is in the range of 0.5 to 0.8. ### Claim 3 (depends on 1) The semiconductor package structure according to claim 1, wherein the trace is disposed adjacent to the at least one pad, the semiconductor chip comprises an Under Bump Metal (UBM), and a side surface of the UBM is substantially coplanar with a side surface of the trace. ### Claim 4 (depends on 1) The semiconductor package structure according to claim 1, wherein the conductive bump is disposed within the circumference of the at least one pad. ### Claim 5 (depends on 1) The semiconductor package structure according to claim 1, wherein the conductive bump covers a portion of the insulating layer. ### Claim 6 (depends on 1) The semiconductor package structure according to claim 1, wherein a width of the accommodating space is greater than the difference between a width of the conductive bump and a width of the at least one pad. ### Claim 7 (depends on 1) The semiconductor package structure according to claim 1, wherein a width of the conductive bump is less than a width of the at least one pad. ### Claim 8 (depends on 1) The semiconductor package structure according to claim 1, wherein the at least one pad has a geometrical central axis, the conductive bump has a geometrical central axis, and there is an offset between the geometrical central axis of the at least one pad and the geometrical central axis of the conductive bump. ### Claim 9 (depends on 1) The semiconductor package structure according to claim 1, wherein the protrusion portion and the at least one pad are formed integrally. ### Claim 10 A semiconductor package structure, comprising: a substrate comprising: an insulating layer having a top surface; a conductive circuit layer recessed from the top surface of the insulating layer, wherein the conductive circuit layer comprises at least one first pad and a trace, and the trace is exposed from the insulating layer; and a first conductive bump disposed on the first pad; a semiconductor chip; and a conductive material electrically connected to the first conductive bump and the semiconductor chip; wherein a part of the conductive material is lower than the top surface of the insulating layer; and wherein the first conductive bump comprises a main portion, a metal layer portion and a protrusion portion, the protrusion portion protrudes from the first pad, the metal layer portion is disposed on the protrusion portion, the main portion is disposed on the metal layer portion, and the widths of the main portion, the metal layer portion and the protrusion portion are substantially the same. ### Claim 11 (depends on 10) The semiconductor package structure according to claim 10, wherein a width of the first conductive bump is less than a width of the first pad, and a side surface of the first conductive bump, a top surface of the first pad and a side surface of the insulating layer define a first accommodating space. ### Claim 12 (depends on 10) The semiconductor package structure according to claim 10, wherein a ratio of a width of the first conductive bump to a width of the first pad is in a range from 0.5 to 0.8. ### Claim 13 (depends on 10) The semiconductor package structure according to claim 10, wherein the substrate further comprises a second conductive bump, and the conductive circuit layer further comprises a second pad, wherein the second conductive bump is disposed on the second pad, a width of the second conductive bump is less than a width of the second pad, a side surface of the second conductive bump, a top surface of the second pad and a side surface of the insulating layer define a second accommodating space, and the trace is disposed between the first pad and the second pad. ### Claim 14 (depends on 10) The semiconductor package structure according to claim 10, wherein the first conductive bump is positioned within a circumference of the first pad. ### Claim 15 (depends on 10) The semiconductor package structure according to claim 10, wherein the first conductive bump covers a portion of the insulating layer. ### Claim 16 (depends on 10) The semiconductor package structure according to claim 10, wherein a width of the first conductive bump is less than a width of the first pad. ### Claim 17 (depends on 10) The semiconductor package structure according to claim 10, wherein the first pad has a geometrical central axis, the first conductive bump has a geometrical central axis, and there is an offset between the geometrical central axis of the first pad and the geometrical central axis of the first conductive bump. ### Claim 18 (depends on 10) The semiconductor package structure according to claim 10, wherein the protrusion portion and the first pad are formed integrally.